From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 31 Mar 2013 09:17:56 +0000 (+0200)
Subject: Added test cases from 2012 paper on comparison of foss verilog synthesis tools
X-Git-Tag: yosys-0.2.0~661
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5640b7d6078a681e33e85f06920394204f41c875;p=yosys.git

Added test cases from 2012 paper on comparison of foss verilog synthesis tools
---

diff --git a/tests/simple/always01.v b/tests/simple/always01.v
new file mode 100644
index 000000000..21379cb01
--- /dev/null
+++ b/tests/simple/always01.v
@@ -0,0 +1,10 @@
+module uut_always01(clock, reset, count);
+
+input clock, reset;
+output [3:0] count;
+reg [3:0] count;
+
+always @(posedge clock)
+	count <= reset ?  0 : count + 1;
+
+endmodule
diff --git a/tests/simple/always02.v b/tests/simple/always02.v
new file mode 100644
index 000000000..8c7ef0fb5
--- /dev/null
+++ b/tests/simple/always02.v
@@ -0,0 +1,13 @@
+module uut_always02(clock, reset, count);
+
+input clock, reset;
+output [3:0] count;
+reg [3:0] count;
+
+always @(posedge clock) begin
+	count <= count + 1;
+	if (reset)
+		count <= 0;
+end
+
+endmodule
diff --git a/tests/simple/always03.v b/tests/simple/always03.v
new file mode 100644
index 000000000..5542175e5
--- /dev/null
+++ b/tests/simple/always03.v
@@ -0,0 +1,22 @@
+module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, out1, out2, out3);
+
+input clock, in1, in2, in3, in4, in5, in6, in7;
+output out1, out2, out3;
+reg out1, out2, out3;
+
+always @(posedge clock) begin
+	out1 = in1;
+	if (in2)
+		out1 = !out1;
+	out2 <= out1;
+	if (in3)
+		out2 <= out2;
+	if (in4)
+		if (in5)
+			out3 <= in6;
+		else
+			out3 <= in7;
+	out1 = out1 ^ out2;
+end
+
+endmodule
diff --git a/tests/simple/arrays01.v b/tests/simple/arrays01.v
new file mode 100644
index 000000000..bd0eda294
--- /dev/null
+++ b/tests/simple/arrays01.v
@@ -0,0 +1,16 @@
+module uut_arrays01(clock, we, addr, wr_data, rd_data);
+
+input clock, we;
+input [3:0] addr, wr_data;
+output [3:0] rd_data;
+reg [3:0] rd_data;
+
+reg [3:0] memory [15:0];
+
+always @(posedge clock) begin
+	if (we)
+		memory[addr] <= wr_data;
+	rd_data <= memory[addr];
+end
+
+endmodule
diff --git a/tests/simple/forgen01.v b/tests/simple/forgen01.v
new file mode 100644
index 000000000..70ee7e667
--- /dev/null
+++ b/tests/simple/forgen01.v
@@ -0,0 +1,20 @@
+module uut_forgen01(a, y);
+
+input [4:0] a;
+output y;
+
+integer i, j;
+reg [31:0] lut;
+
+initial begin
+	for (i = 0; i < 32; i = i+1) begin
+		lut[i] = i > 1;
+		for (j = 2; j*j <= i; j = j+1)
+			if (i % j == 0)
+				lut[i] = 0;
+	end
+end
+
+assign y = lut[a];
+
+endmodule
diff --git a/tests/simple/forgen02.v b/tests/simple/forgen02.v
new file mode 100644
index 000000000..14af070c3
--- /dev/null
+++ b/tests/simple/forgen02.v
@@ -0,0 +1,30 @@
+module uut_forgen02(a, b, cin, y, cout);
+
+parameter WIDTH = 8;
+
+input [WIDTH-1:0] a, b;
+input cin;
+
+output [WIDTH-1:0] y;
+output cout;
+
+genvar i;
+wire [WIDTH-1:0] carry;
+
+generate
+	for (i = 0; i < WIDTH; i=i+1) begin:adder
+		wire [2:0] D;
+		assign D[1:0] = { a[i], b[i] };
+		if (i == 0) begin:chain
+			assign D[2] = cin;
+		end else begin:chain
+			assign D[2] = carry[i-1];
+		end
+		assign y[i] = ^D;
+		assign carry[i] = &D[1:0] | (^D[1:0] & D[2]);
+	end
+endgenerate
+
+assign cout = carry[WIDTH-1];
+
+endmodule