From: Kenneth Graunke <kenneth@whitecape.org>
Date: Wed, 24 May 2017 04:33:12 +0000 (-0700)
Subject: anv: Port over CACHE_MODE_1 optimization fix enables from brw.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56535959fd5acf1066506d6387adb16d86d4c65c;p=mesa.git

anv: Port over CACHE_MODE_1 optimization fix enables from brw.

Ben and I haven't observed these to help anything, but they enable
hardware optimizations for particular cases.  It's probably best to
enable them ahead of time, before we run into such a case.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index bf1217bbcdc..00c4105a825 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -52,6 +52,19 @@ genX(init_device_state)(struct anv_device *device)
       ps.PipelineSelection = _3D;
    }
 
+#if GEN_GEN >= 9
+   uint32_t cache_mode_1;
+   anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
+                   .PartialResolveDisableInVC = true,
+                   .PartialResolveDisableInVCMask = true,
+                   .FloatBlendOptimizationEnable = true,
+                   .FloatBlendOptimizationEnableMask = true);
+   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+      lri.RegisterOffset = GENX(CACHE_MODE_1_num);
+      lri.DataDWord      = cache_mode_1;
+   }
+#endif
+
    anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
 
    anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {