From: Luke Kenneth Casson Leighton Date: Thu, 11 Nov 2021 16:10:07 +0000 (+0000) Subject: TODO, implement is_dcbz X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5663a0ac7d10df8df27b55f8128a08e62078acbe;p=soc.git TODO, implement is_dcbz --- diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 20695273..9dc133ab 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -343,7 +343,7 @@ class TestMemoryPortInterface(PortInterfaceBase): # hard-code memory addressing width to 6 bits self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False) - def set_wr_addr(self, m, addr, mask, misalign, msr_pr): + def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): lsbaddr, msbaddr = self.splitaddr(addr) m.d.comb += self.mem.wrport.addr.eq(msbaddr)