From: Rob Clark <robdclark@chromium.org>
Date: Tue, 7 May 2019 13:05:58 +0000 (-0700)
Subject: freedreno/ir3: split out const_state setup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5690f83bb533cd62747194f0029892e9dc662669;p=mesa.git

freedreno/ir3: split out const_state setup

Next patch moves const_state to ir3_shader, before the compile context
is created.  So move the code around in prep to call it earlier.

Signed-off-by: Rob Clark <robdclark@chromium.org>
---

diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c
index d2210184a60..5b95373b675 100644
--- a/src/freedreno/ir3/ir3_context.c
+++ b/src/freedreno/ir3/ir3_context.c
@@ -24,8 +24,6 @@
  *    Rob Clark <robclark@freedesktop.org>
  */
 
-#include "util/u_math.h"
-
 #include "ir3_compiler.h"
 #include "ir3_context.h"
 #include "ir3_image.h"
@@ -103,53 +101,7 @@ ir3_context_init(struct ir3_compiler *compiler,
 
 	ir3_ibo_mapping_init(&so->image_mapping, ctx->s->info.num_textures);
 
-	struct ir3_const_state *const_state = &so->const_state;
-	memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
-
-	ir3_nir_scan_driver_consts(ctx->s, const_state);
-
-	const_state->num_uniforms = ctx->s->num_uniforms;
-	const_state->num_ubos = ctx->s->info.num_ubos;
-
-	debug_assert((ctx->so->shader->ubo_state.size % 16) == 0);
-	unsigned constoff = align(ctx->so->shader->ubo_state.size / 16, 4);
-	unsigned ptrsz = ir3_pointer_size(ctx->compiler);
-
-	if (const_state->num_ubos > 0) {
-		const_state->offsets.ubo = constoff;
-		constoff += align(ctx->s->info.num_ubos * ptrsz, 4) / 4;
-	}
-
-	if (const_state->ssbo_size.count > 0) {
-		unsigned cnt = const_state->ssbo_size.count;
-		const_state->offsets.ssbo_sizes = constoff;
-		constoff += align(cnt, 4) / 4;
-	}
-
-	if (const_state->image_dims.count > 0) {
-		unsigned cnt = const_state->image_dims.count;
-		const_state->offsets.image_dims = constoff;
-		constoff += align(cnt, 4) / 4;
-	}
-
-	unsigned num_driver_params = 0;
-	if (so->type == MESA_SHADER_VERTEX) {
-		num_driver_params = IR3_DP_VS_COUNT;
-	} else if (so->type == MESA_SHADER_COMPUTE) {
-		num_driver_params = IR3_DP_CS_COUNT;
-	}
-
-	const_state->offsets.driver_param = constoff;
-	constoff += align(num_driver_params, 4) / 4;
-
-	if ((so->type == MESA_SHADER_VERTEX) &&
-			(compiler->gpu_id < 500) &&
-			so->shader->stream_output.num_outputs > 0) {
-		const_state->offsets.tfbo = constoff;
-		constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
-	}
-
-	const_state->offsets.immediate = constoff;
+	ir3_setup_const_state(so);
 
 	return ctx;
 }
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 804196f63e9..edb5490d664 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -26,6 +26,7 @@
 
 
 #include "util/debug.h"
+#include "util/u_math.h"
 
 #include "ir3_nir.h"
 #include "ir3_compiler.h"
@@ -276,7 +277,7 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 	return s;
 }
 
-void
+static void
 ir3_nir_scan_driver_consts(nir_shader *shader,
 		struct ir3_const_state *layout)
 {
@@ -328,3 +329,59 @@ ir3_nir_scan_driver_consts(nir_shader *shader,
 		}
 	}
 }
+
+void
+ir3_setup_const_state(struct ir3_shader_variant *v)
+{
+	struct ir3_shader *shader = v->shader;
+	struct ir3_compiler *compiler = shader->compiler;
+	struct ir3_const_state *const_state = &v->const_state;
+	nir_shader *nir = shader->nir;
+
+	memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
+
+	ir3_nir_scan_driver_consts(nir, const_state);
+
+	const_state->num_uniforms = nir->num_uniforms;
+	const_state->num_ubos = nir->info.num_ubos;
+
+	debug_assert((shader->ubo_state.size % 16) == 0);
+	unsigned constoff = align(shader->ubo_state.size / 16, 4);
+	unsigned ptrsz = ir3_pointer_size(compiler);
+
+	if (const_state->num_ubos > 0) {
+		const_state->offsets.ubo = constoff;
+		constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
+	}
+
+	if (const_state->ssbo_size.count > 0) {
+		unsigned cnt = const_state->ssbo_size.count;
+		const_state->offsets.ssbo_sizes = constoff;
+		constoff += align(cnt, 4) / 4;
+	}
+
+	if (const_state->image_dims.count > 0) {
+		unsigned cnt = const_state->image_dims.count;
+		const_state->offsets.image_dims = constoff;
+		constoff += align(cnt, 4) / 4;
+	}
+
+	unsigned num_driver_params = 0;
+	if (shader->type == MESA_SHADER_VERTEX) {
+		num_driver_params = IR3_DP_VS_COUNT;
+	} else if (shader->type == MESA_SHADER_COMPUTE) {
+		num_driver_params = IR3_DP_CS_COUNT;
+	}
+
+	const_state->offsets.driver_param = constoff;
+	constoff += align(num_driver_params, 4) / 4;
+
+	if ((shader->type == MESA_SHADER_VERTEX) &&
+			(compiler->gpu_id < 500) &&
+			shader->stream_output.num_outputs > 0) {
+		const_state->offsets.tfbo = constoff;
+		constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
+	}
+
+	const_state->offsets.immediate = constoff;
+}
diff --git a/src/freedreno/ir3/ir3_nir.h b/src/freedreno/ir3/ir3_nir.h
index bc0d496adfb..6cfe27a56b2 100644
--- a/src/freedreno/ir3/ir3_nir.h
+++ b/src/freedreno/ir3/ir3_nir.h
@@ -33,8 +33,6 @@
 
 #include "ir3_shader.h"
 
-void ir3_nir_scan_driver_consts(nir_shader *shader, struct ir3_const_state *layout);
-
 bool ir3_nir_apply_trig_workarounds(nir_shader *shader);
 bool ir3_nir_lower_tg4_to_tex(nir_shader *shader);
 bool ir3_nir_lower_io_offsets(nir_shader *shader);
@@ -52,4 +50,6 @@ bool ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader *shader);
 nir_ssa_def *
 ir3_nir_try_propagate_bit_shift(nir_builder *b, nir_ssa_def *offset, int32_t shift);
 
+void ir3_setup_const_state(struct ir3_shader_variant *v);
+
 #endif /* IR3_NIR_H_ */