From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Jun 2020 18:32:46 +0000 (+0100)
Subject: reduce instruction depth to 6 bits in TestIssuer
X-Git-Tag: div_pipeline~355
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=569befdf99da179cf5a272bf360c57ae05ad3107;p=soc.git

reduce instruction depth to 6 bits in TestIssuer
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 66f1245e..0b6ea0cb 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -315,7 +315,7 @@ class TestIssuer(Elaboratable):
 
     efficiency and speed is not the main goal here: functional correctness is.
     """
-    def __init__(self, addrwid=6, idepth=16):
+    def __init__(self, addrwid=6, idepth=6):
         # main instruction core
         self.core = core = NonProductionCore(addrwid)
 
diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 7e13dfe8..3382cce4 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -33,7 +33,6 @@ from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
 
 def setup_regs(core, test):
 
-
     # set up INT regfile, "direct" write (bypass rd/write ports)
     intregs = core.regs.int
     for i in range(32):
@@ -71,6 +70,7 @@ def setup_regs(core, test):
         yield xregs.regs[xregs.CA].reg.eq(0)
 
     # XER
+    pdecode2 = core.pdecode2
     so = yield xregs.regs[xregs.SO].reg
     ov = yield xregs.regs[xregs.OV].reg
     ca = yield xregs.regs[xregs.CA].reg