From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Jul 2019 21:18:36 +0000 (-0700)
Subject: Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
X-Git-Tag: working-ls180~1039^2~357
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=569cd66764f43af9ea73038ce7437ab8557d497e;p=yosys.git

Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
---

569cd66764f43af9ea73038ce7437ab8557d497e
diff --cc techlibs/xilinx/cells_sim.v
index 5410983ae,ea5a3b788..1262fc8c1
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -516,12 -506,6 +516,12 @@@ module DSP48E1 
          if (PCIN != 48'b0)          $fatal(1, "Unsupported PCIN value");
          if (CARRYIN != 1'b0)        $fatal(1, "Unsupported CARRYIN value");
  `endif
-         Pr[42:0] <= Ar[24:0] * Br;
 -        P[42:0] <= $signed(A[24:0]) * $signed(B);
++        Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br);
      end
 +
 +    generate
 +        if (PREG == 1) begin always @(posedge CLK) if (CEP) P <= Pr; end
 +        else           always @* P <= Pr;
 +    endgenerate
 +
  endmodule
diff --cc techlibs/xilinx/dsp_map.v
index da1d6f3a9,000000000..2063c45e2
mode 100644,000000..100644
--- a/techlibs/xilinx/dsp_map.v
+++ b/techlibs/xilinx/dsp_map.v
@@@ -1,40 -1,0 +1,40 @@@
- module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
++module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y);
 +	wire [47:0] P_48;
 +	DSP48E1 #(
 +		// Disable all registers
 +		.ACASCREG(0),
 +		.ADREG(0),
 +		.A_INPUT("DIRECT"),
 +		.ALUMODEREG(0),
 +		.AREG(0),
 +		.BCASCREG(0),
 +		.B_INPUT("DIRECT"),
 +		.BREG(0),
 +		.CARRYINREG(0),
 +		.CARRYINSELREG(0),
 +		.CREG(0),
 +		.DREG(0),
 +		.INMODEREG(0),
 +		.MREG(0),
 +		.OPMODEREG(0),
 +		.PREG(0)
 +	) _TECHMAP_REPLACE_ (
 +		//Data path
- 		.A({5'b0, A}),
- 		.B(B),
++		.A({6'b0, A}),
++		.B({1'b0, B}),
 +		.C(48'b0),
 +		.D(24'b0),
 +		.P(P_48),
 +
 +		.INMODE(4'b0000),
 +		.ALUMODE(4'b0000),
 +		.OPMODE(7'b000101),
 +		.CARRYINSEL(3'b000),
 +
 +		.ACIN(30'b0),
 +		.BCIN(18'b0),
 +		.PCIN(48'b0),
 +		.CARRYIN(1'b0)
 +	);
 +	assign Y = P_48;
 +endmodule