From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 9 Oct 2008 07:04:36 +0000 (-0700)
Subject: X86: Make far ret modify CS instead of some random selector.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=569db520ad69bc8b3f506accb0a86d1e519e63ad;p=gem5.git

X86: Make far ret modify CS instead of some random selector.
---

diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
index b18d48264..d1a8245e6 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
@@ -109,8 +109,8 @@ processDescriptor:
     chks t2, t3, IretCheck, dataSize=8
     # There should be validity checks on the RIP checks here, but I'll do
     # that later.
-    wrdl reg, t3, t2
-    wrsel reg, t2
+    wrdl cs, t3, t2
+    wrsel cs, t2
     wrip t0, t1
     bri t0, label("end")