From: lkcl <lkcl@web>
Date: Wed, 10 May 2023 13:21:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56a9d942991c6ad48ddd92fbe098eb66a64d621e;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 1aa504f6d..bedbfa602 100644
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -283,6 +283,11 @@ and have more akin with their x86 equivalents.
 >And this is for a feature that would be rarely used and is redundant. 
 ```
 
+Further down an additional author observes that Operand-Forwarding mitigates this
+problem but sufficient "advance notice" is needed.  An inline-assembler chained
+sequence such as those **required** for bigint would be considered such and
+thus the high cost may be avoided.
+
 ## fclass and GPR-FPR moves
 
 [[sv/fclass]] - just one instruction.  With SFFS being locked down to