From: Luke Kenneth Casson Leighton Date: Tue, 27 Nov 2018 00:20:06 +0000 (+0000) Subject: split cpu loadstore calc out X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56b1de0ace7ac7f5e1e0c5211a025ce15a24a365;p=rv32.git split cpu loadstore calc out --- diff --git a/cpu.py b/cpu.py index bdf234d..01b4e23 100644 --- a/cpu.py +++ b/cpu.py @@ -290,16 +290,6 @@ class CPU(Module): """ """ - def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): - """ returns whether a load/store is misaligned - """ - return Case(funct3[:2], - { F3.sb: ls.eq(Constant(0)), - F3.sh: ls.eq(load_store_address_low_2[0] != 0), - F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)), - "default": ls.eq(Constant(1)) - }) - def get_lsbm(self, dc): return Cat(Constant(1), Mux((dc.funct3[1] | dc.funct3[0]), @@ -513,24 +503,6 @@ class CPU(Module): self.write_register(dc.rd, csr_output_value) )] - """ - `csr_mip: begin - csr_output_value = 0; - csr_output_value[11] = mip_meip; - csr_output_value[9] = mip_seip; - csr_output_value[8] = mip_ueip; - csr_output_value[7] = mip_mtip; - csr_output_value[5] = mip_stip; - csr_output_value[4] = mip_utip; - csr_output_value[3] = mip_msip; - csr_output_value[1] = mip_ssip; - csr_output_value[0] = mip_usip; - end - endcase - end - endcase - end - """ def __init__(self): Module.__init__(self) self.clk = ClockSignal() @@ -632,16 +604,23 @@ class CPU(Module): load_store_address = Signal(32) load_store_address_low_2 = Signal(2) - - self.comb += load_store_address.eq(dc.immediate + self.regs.rs1) - self.comb += load_store_address_low_2.eq( - dc.immediate[:2] + self.regs.rs1[:2]) - load_store_misaligned = Signal() + unmasked_loaded_value = Signal(32) + loaded_value = Signal(32) - lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3, - load_store_address_low_2) - self.comb += lsa + lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc", + i_dc_immediate = dc.immediate, + i_dc_funct3 = dc.funct3, + i_rs1 = self.regs.rs1, + i_rs2 = self.regs.rs2, + i_rw_data_in = mi.rw_data_in, + i_rw_data_out = mi.rw_data_out, + o_load_store_address = load_store_address, + o_load_store_address_low_2 = load_store_address_low_2, + o_load_store_misaligned = load_store_misaligned, + o_loaded_value = loaded_value) + + self.specials += lsc # XXX rwaddr not 31:2 any more self.comb += mi.rw_address.eq(load_store_address[2:]) @@ -656,50 +635,6 @@ class CPU(Module): _Operator("<<", [unshifted_load_store_byte_mask, load_store_address_low_2])) - # XXX not obvious - b3 = Mux(load_store_address_low_2[1], - Mux(load_store_address_low_2[0], self.regs.rs2[0:8], - self.regs.rs2[8:16]), - Mux(load_store_address_low_2[0], self.regs.rs2[16:24], - self.regs.rs2[24:32])) - b2 = Mux(load_store_address_low_2[1], self.regs.rs2[0:8], - self.regs.rs2[16:24]) - b1 = Mux(load_store_address_low_2[0], self.regs.rs2[0:8], - self.regs.rs2[8:16]) - b0 = self.regs.rs2[0:8] - - self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3)) - - # XXX not obvious - unmasked_loaded_value = Signal(32) - - b0 = Mux(load_store_address_low_2[1], - Mux(load_store_address_low_2[0], mi.rw_data_out[24:32], - mi.rw_data_out[16:24]), - Mux(load_store_address_low_2[0], mi.rw_data_out[15:8], - mi.rw_data_out[0:8])) - b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31], - mi.rw_data_out[8:16]) - b23 = mi.rw_data_out[16:32] - - self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23)) - - # XXX not obvious - loaded_value = Signal(32) - - b0 = unmasked_loaded_value[0:8] - b1 = Mux(dc.funct3[0:2] == 0, - Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8), - unmasked_loaded_value[8:16]) - b2 = Mux(dc.funct3[1] == 0, - Replicate(~dc.funct3[2] & - Mux(dc.funct3[0], unmasked_loaded_value[15], - unmasked_loaded_value[7]), - 16), - unmasked_loaded_value[16:32]) - - self.comb += loaded_value.eq(Cat(b0, b1, b2)) - self.comb += mi.rw_active.eq(~self.reset & (ft.output_state == FOS.valid) & ~load_store_misaligned diff --git a/cpu_loadstore_calc.py b/cpu_loadstore_calc.py index 1781af0..5a82a0d 100644 --- a/cpu_loadstore_calc.py +++ b/cpu_loadstore_calc.py @@ -56,7 +56,6 @@ class CPULoadStoreCalc(Module): self.dc_funct3 = Signal(3) self.rs1 = Signal(32) self.rs2 = Signal(32) - self.rw_address = Signal(32) self.rw_data_in = Signal(32) self.rw_data_out = Signal(32) @@ -73,9 +72,6 @@ class CPULoadStoreCalc(Module): self.load_store_address_low_2) self.comb += lsa - # XXX rwaddr not 31:2 any more - self.comb += self.rw_address.eq(self.load_store_address[2:]) - # XXX not obvious b3 = Mux(self.load_store_address_low_2[1], Mux(self.load_store_address_low_2[0], self.rs2[0:8], @@ -128,7 +124,6 @@ if __name__ == "__main__": example.dc_funct3, example.rs1, example.rs2, - example.rw_address, example.rw_data_in, example.rw_data_out, example.load_store_address,