From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 24 Nov 2014 13:39:24 +0000 (+0100)
Subject: Fixed two minor bugs in constant parsing
X-Git-Tag: yosys-0.5~270
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56c7d1e266cf6b2f9bfcb9f76f2ddf388ddc51ea;p=yosys.git

Fixed two minor bugs in constant parsing
---

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index ca995915f..735bc5f99 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -182,7 +182,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
 	if (str == endptr)
 		len_in_bits = -1;
 
-	// The "<bits>'s?[bodh]<digits>" syntax
+	// The "<bits>'s?[bodhBODH]<digits>" syntax
 	if (*endptr == '\'')
 	{
 		std::vector<RTLIL::State> data;
@@ -194,15 +194,19 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
 		switch (*(endptr+1))
 		{
 		case 'b':
+		case 'B':
 			my_strtobin(data, endptr+2, len_in_bits, 2, case_type);
 			break;
 		case 'o':
+		case 'O':
 			my_strtobin(data, endptr+2, len_in_bits, 8, case_type);
 			break;
 		case 'd':
+		case 'D':
 			my_strtobin(data, endptr+2, len_in_bits, 10, case_type);
 			break;
 		case 'h':
+		case 'H':
 			my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
 			break;
 		default:
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 5e739842b..c3dfa8b92 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -177,12 +177,12 @@ YOSYS_NAMESPACE_END
 "genvar"  { return TOK_GENVAR; }
 "real"    { return TOK_REAL; }
 
-[0-9]+ {
+[0-9][0-9_]* {
 	frontend_verilog_yylval.string = new std::string(yytext);
 	return TOK_CONST;
 }
 
-[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
+[0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
 	frontend_verilog_yylval.string = new std::string(yytext);
 	return TOK_CONST;
 }