From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 15 May 2021 16:38:03 +0000 (+0100)
Subject: add fp mv test, correct pseudocode
X-Git-Tag: 0.0.3~24
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56cffc2aecafe55017990a9a26e7ffdcfb255b5f;p=openpower-isa.git

add fp mv test, correct pseudocode
---

diff --git a/openpower/isa/fpmove.mdwn b/openpower/isa/fpmove.mdwn
index a30cdb39..5247e834 100644
--- a/openpower/isa/fpmove.mdwn
+++ b/openpower/isa/fpmove.mdwn
@@ -11,7 +11,7 @@ X-Form
 
 Pseudo-code:
 
-    FRT <- FRB
+    FRT <- FRB[0:63]
 
 Special Registers Altered:
 
@@ -26,8 +26,7 @@ X-Form
 
 Pseudo-code:
 
-    FRT <- FRB
-    FRT[0] <- 0b0
+    FRT <- 0b0 || FRB[1:63]
 
 Special Registers Altered:
 
@@ -42,8 +41,7 @@ X-Form
 
 Pseudo-code:
 
-    FRT <- FRB
-    FRT[0] <- 0b1
+    FRT[0] <- 0b1 || FRB[1:63]
 
 Special Registers Altered:
 
@@ -58,8 +56,7 @@ X-Form
 
 Pseudo-code:
 
-    FRT <- FRB
-    FRT[0] <- ¬FRB[0]
+    FRT <- ¬FRB[0] || FRB[1:63]
 
 Special Registers Altered:
 
@@ -74,8 +71,7 @@ X-Form
 
 Pseudo-code:
 
-    FRT <- FRB
-    FRT[0] <- FRA[0]
+    FRT <- FRA[0] || FRB[1:63]
 
 Special Registers Altered:
 
diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 9434f6ae..c0e384df 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -22,7 +22,7 @@ class DecoderTestCase(FHDLTestCase):
         for i in range(32):
             self.assertEqual(sim.fpr(i), SelectableInt(expected_fpr[i], 64))
 
-    def tst_fpload(self):
+    def test_fpload(self):
         """>>> lst = ["lfsx 1, 0, 0",
                      ]
         """
@@ -38,7 +38,7 @@ class DecoderTestCase(FHDLTestCase):
             print("FPR 1", sim.fpr(1))
             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
 
-    def tst_fp_single_ldst(self):
+    def test_fp_single_ldst(self):
         """>>> lst = ["lfsx 1, 1, 0",   # load fp 1 from mem location 0
                       "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA
                       "lfsu 2, 0(1)",   # re-load from UPDATED r1
@@ -79,6 +79,23 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 
+    def test_fp_mv(self):
+        """>>> lst = ["fmr 1, 2",
+                     ]
+        """
+        lst = ["fneg 1, 2",
+                     ]
+
+        fprs = [0] * 32
+        fprs[2] = 0x4040266660000000
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            print("FPR 1", sim.fpr(1))
+            print("FPR 2", sim.fpr(2))
+            self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
+
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None,
                               initial_fprs=None):