From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 26 Mar 2020 16:56:53 +0000 (+0000)
Subject: fix 1-overflow
X-Git-Tag: div_pipeline~1621
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56d145e42ac75626423915af22d1493f1e7bb143;p=soc.git

fix 1-overflow
---

diff --git a/src/soc/simulator/internalop_sim.py b/src/soc/simulator/internalop_sim.py
index c794e591..d4c1c8d6 100644
--- a/src/soc/simulator/internalop_sim.py
+++ b/src/soc/simulator/internalop_sim.py
@@ -59,6 +59,8 @@ class RegFile:
         self.sprs = {}
 
     def write_reg(self, regnum, value):
+        all1s = (1<<64)-1 # 64 bits worth of 1s
+        value &= all1s
         print("Writing {:x} to reg r{}".format(value, regnum))
         self.regfile[regnum] = value
 
@@ -102,6 +104,7 @@ class InternalOpSimulator:
             assert False, "Not implemented"
 
     def alu_op(self, pdecode2):
+        all1s = (1<<64)-1 # 64 bits worth of 1s
         internal_op = yield pdecode2.dec.op.internal_op
         operand1 = 0
         operand2 = 0
@@ -125,7 +128,7 @@ class InternalOpSimulator:
 
         inv_a = yield pdecode2.dec.op.inv_a
         if inv_a:
-            operand1 = (~operand1) & ((1<<64)-1)
+            operand1 = (~operand1) & all1s
 
         cry_in = yield pdecode2.dec.op.cry_in
         if cry_in == CryIn.ONE.value: