From: Anuj Phogat Date: Wed, 7 Feb 2018 01:09:09 +0000 (-0800) Subject: intel/compiler: Memory fence commit must always be enabled for gen10+ X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56dc9f9f49638e0769d6bc696ff7f5dafccec9fc;p=mesa.git intel/compiler: Memory fence commit must always be enabled for gen10+ Commit bit in the message descriptor (Bit 13) must be always set to true in CNL+ for memory fence messages. It also fixes a piglit GPU hang on cnl+ in simulation environment. Piglit test: arb_shader_image_load_store-shader-mem-barrier See HSD ES # 1404612949 Signed-off-by: Anuj Phogat Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Francisco Jerez --- diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 44abede16bc..f8102e014e5 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3287,7 +3287,9 @@ brw_memory_fence(struct brw_codegen *p, struct brw_reg dst) { const struct gen_device_info *devinfo = p->devinfo; - const bool commit_enable = devinfo->gen == 7 && !devinfo->is_haswell; + const bool commit_enable = + devinfo->gen >= 10 || /* HSD ES # 1404612949 */ + (devinfo->gen == 7 && !devinfo->is_haswell); struct brw_inst *insn; brw_push_insn_state(p);