From: lkcl Date: Fri, 3 Jun 2022 14:01:41 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1999 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56ded15e6fd8aac0c09b1aab41ef02202298463e;p=libreriscv.git --- diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 5ff58ff39..b586d82bc 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -79,9 +79,11 @@ Arithmetic (known as "normal" mode) is where Scalar and Parallel Reduction can be done: Saturation as well, and two new innovative modes for Vector ISAs: data-dependent fail-first and predicate result. Reduction and Saturation are common to see in Vector ISAs: it is just -that they are usually added as explicit instructions. In SVP64 these +that they are usually added as explicit instructions, +and NEC SX Aurora has even more iterative instructions. In SVP64 these concepts are applied in the abstract general form, which takes some -getting used to, as it may result in invalid results, but ultimately +getting used to, as it may, when applied to non-commutative +instructions incorrectly, result in invalid results, but ultimately it is critical to think in terms of the "rules", that everything is Scalar instructions in strict Program Order.