From: Andreas Sandberg Date: Mon, 7 Sep 2020 11:34:02 +0000 (+0100) Subject: base, sim, mem, arch: Remove the dummy CPU in NULL X-Git-Tag: develop-gem5-snapshot~764 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56e53cafe0e68551f456c1da85913022704e573b;p=gem5.git base, sim, mem, arch: Remove the dummy CPU in NULL The NULL ISA target has a dummy BaseCPU class that doesn't seem to be needed anymore. Remove this class and the some unnecessary includes. Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34236 Reviewed-by: Jason Lowe-Power Reviewed-by: Gabe Black Reviewed-by: Daniel Carvalho Tested-by: kokoro --- diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 8400ed6f4..153a991b6 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -50,6 +50,7 @@ #include "arch/registers.hh" #include "base/logging.hh" #include "base/trace.hh" +#include "cpu/base.hh" #include "debug/LLSC.hh" #include "mem/packet.hh" #include "mem/request.hh" diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript index 41457e2ef..3f0b0531a 100644 --- a/src/arch/null/SConscript +++ b/src/arch/null/SConscript @@ -36,6 +36,3 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Import('*') - -if env['TARGET_ISA'] == 'null': - Source('cpu_dummy.cc') diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc deleted file mode 100644 index df30b81e7..000000000 --- a/src/arch/null/cpu_dummy.cc +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2013 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * Provide the actual storage for maxThreadsPerCPU which is declared - * extern and normally provided by src/cpu/base.cc - */ -int maxThreadsPerCPU = 1; diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh deleted file mode 100644 index 7e183eb2b..000000000 --- a/src/arch/null/cpu_dummy.hh +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2013 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARCH_NULL_CPU_DUMMY_HH__ -#define __ARCH_NULL_CPU_DUMMY_HH__ - -#include "sim/core.hh" - -class BaseCPU -{ - public: - static int numSimulatedInsts() { return 0; } - static int numSimulatedOps() { return 0; } - static void wakeup(ThreadID tid) { ; } -}; - -#endif // __ARCH_NULL_CPU_DUMMY_HH__ diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh index fd45b3f6c..10d1839d8 100644 --- a/src/arch/riscv/locked_mem.hh +++ b/src/arch/riscv/locked_mem.hh @@ -52,6 +52,7 @@ #include "arch/registers.hh" #include "base/logging.hh" #include "base/trace.hh" +#include "cpu/base.hh" #include "debug/LLSC.hh" #include "mem/packet.hh" #include "mem/request.hh" diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 53204929c..c830576ad 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -48,7 +48,7 @@ // and if so stop here #include "config/the_isa.hh" #if THE_ISA == NULL_ISA -#include "arch/null/cpu_dummy.hh" +#error Including BaseCPU in a system without CPU support #else #include "arch/generic/interrupts.hh" #include "base/statistics.hh" diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc index a5730c78d..79f716c34 100644 --- a/src/mem/abstract_mem.cc +++ b/src/mem/abstract_mem.cc @@ -45,7 +45,6 @@ #include "arch/locked_mem.hh" #include "base/loader/memory_image.hh" #include "base/loader/object_file.hh" -#include "cpu/base.hh" #include "cpu/thread_context.hh" #include "debug/LLSC.hh" #include "debug/MemoryAccess.hh" diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index a35be335a..2ff466b6a 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -48,7 +48,6 @@ #include #include "base/intmath.hh" -#include "cpu/base.hh" #include "mem/cache/base.hh" #include "params/BasePrefetcher.hh" #include "sim/system.hh" diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc index 9464c0d0d..075be5b05 100644 --- a/src/sim/stat_control.cc +++ b/src/sim/stat_control.cc @@ -53,7 +53,10 @@ #include "base/hostinfo.hh" #include "base/statistics.hh" #include "base/time.hh" +#include "config/the_isa.hh" +#if THE_ISA != NULL_ISA #include "cpu/base.hh" +#endif #include "sim/global_event.hh" using namespace std; @@ -109,7 +112,6 @@ struct Global Global::Global() { simInsts - .functor(BaseCPU::numSimulatedInsts) .name("sim_insts") .desc("Number of instructions simulated") .precision(0) @@ -117,13 +119,20 @@ Global::Global() ; simOps - .functor(BaseCPU::numSimulatedOps) .name("sim_ops") .desc("Number of ops (including micro ops) simulated") .precision(0) .prereq(simOps) ; +#if THE_ISA != NULL_ISA + simInsts.functor(BaseCPU::numSimulatedInsts); + simOps.functor(BaseCPU::numSimulatedOps); +#else + simInsts.functor([] { return 0; }); + simOps.functor([] { return 0; }); +#endif + simSeconds .name("sim_seconds") .desc("Number of seconds simulated") diff --git a/src/sim/system.cc b/src/sim/system.cc index cb412a866..cbc30a903 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -50,12 +50,15 @@ #include "base/loader/symtab.hh" #include "base/str.hh" #include "base/trace.hh" +#include "config/the_isa.hh" #include "config/use_kvm.hh" #if USE_KVM #include "cpu/kvm/base.hh" #include "cpu/kvm/vm.hh" #endif +#if THE_ISA != NULL_ISA #include "cpu/base.hh" +#endif #include "cpu/thread_context.hh" #include "debug/Loader.hh" #include "debug/Quiesce.hh" diff --git a/src/sim/system.hh b/src/sim/system.hh index 7d77c48dd..fc93b85f7 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -52,7 +52,6 @@ #include "base/loader/symtab.hh" #include "base/statistics.hh" #include "config/the_isa.hh" -#include "cpu/base.hh" #include "cpu/pc_event.hh" #include "enums/MemoryMode.hh" #include "mem/mem_requestor.hh"