From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Sun, 30 Jan 2022 19:48:50 +0000 (+0100)
Subject: verilog backend: Emit a `wire` for ports as well.
X-Git-Tag: yosys-0.14~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56e7791760ce67cb1831691460b50bf73a4f5117;p=yosys.git

verilog backend: Emit a `wire` for ports as well.

Fixes #3177.
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 32003cf54..aa1d4558c 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -432,7 +432,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 			dump_const(f, wire->attributes.at(ID::init));
 		}
 		f << stringf(";\n");
-	} else if (!wire->port_input && !wire->port_output)
+	} else
 		f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
 #endif
 }