From: Luke Kenneth Casson Leighton Date: Sat, 30 Jul 2022 17:10:12 +0000 (+0100) Subject: add LDST-2P-*PU.csv, tracked down weirdness, it was the X-Git-Tag: sv_maxu_works-initial~194 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56e95f3480d953fb959d4eb43a6b9d1598f8fc5a;p=openpower-isa.git add LDST-2P-*PU.csv, tracked down weirdness, it was the BREV versions of LDST which need removing (not now) --- diff --git a/openpower/isatables/LDSTRM-2P-1S1D-PU.csv b/openpower/isatables/LDSTRM-2P-1S1D-PU.csv new file mode 100644 index 00000000..37b384aa --- /dev/null +++ b/openpower/isatables/LDSTRM-2P-1S1D-PU.csv @@ -0,0 +1,9 @@ +insn,mode,CONDITIONS,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,PU,out2 +lwz,LDST,~SVP64BREV,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0 +lbz,LDST,~SVP64BREV,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0 +lhz,LDST,~SVP64BREV,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0 +lha,LDST,~SVP64BREV,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0 +lfs,LDST,~SVP64BREV,2P,EXTRA2,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,1,0 +lfd,LDST,~SVP64BREV,2P,EXTRA2,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,1,0 +ld,LDST,,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0 +lwa,LDST,,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0 diff --git a/openpower/isatables/LDSTRM-2P-2S-PU.csv b/openpower/isatables/LDSTRM-2P-2S-PU.csv new file mode 100644 index 00000000..8da7965b --- /dev/null +++ b/openpower/isatables/LDSTRM-2P-2S-PU.csv @@ -0,0 +1,7 @@ +insn,mode,CONDITIONS,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,PU,out2 +stw,LDST,,2P,EXTRA2,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,1,0 +stb,LDST,,2P,EXTRA2,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,1,0 +sth,LDST,,2P,EXTRA2,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,1,0 +stfs,LDST,,2P,EXTRA2,s:FRS,s:RA,0,0,RA_OR_ZERO,0,FRS,0,0,0,1,0 +stfd,LDST,,2P,EXTRA2,s:FRS,s:RA,0,0,RA_OR_ZERO,0,FRS,0,0,0,1,0 +std,LDST,,2P,EXTRA2,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,1,0 diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index df35ebd6..40df7920 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -529,7 +529,12 @@ def process_csvs(format): # sigh now the fun begins. this isn't the sanest way to do it # but the patterns are pretty regular. - if value == 'LDSTRM-2P-1S1D': + if value == 'LDSTRM-2P-1S1D-PU': # pack/unpack LD + res['Etype'] = 'EXTRA2' # RM EXTRA2 type + res['0'] = dRT # RT: Rdest_EXTRA2 + res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 + + elif value == 'LDSTRM-2P-1S1D': res['Etype'] = 'EXTRA3' # RM EXTRA3 type res['0'] = dRT # RT: Rdest_EXTRA3 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3 @@ -540,12 +545,18 @@ def process_csvs(format): res['1'] = 'd:RA' # RA: Rdest2_EXTRA2 res['2'] = 's:RA' # RA: Rsrc1_EXTRA2 - elif value == 'LDSTRM-2P-2S': + elif value == 'LDSTRM-2P-2S-PU': # pack/unpack ST # stw, std, sth, stb - res['Etype'] = 'EXTRA3' # RM EXTRA2 type + res['Etype'] = 'EXTRA2' # RM EXTRA2 type res['0'] = sRS # RS: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 + elif value == 'LDSTRM-2P-2S': + # stw, std, sth, stb + res['Etype'] = 'EXTRA3' # RM EXTRA3 type + res['0'] = sRS # RS: Rdest1_EXTRA3 + res['1'] = 's:RA' # RA: Rsrc1_EXTRA3 + elif value == 'LDSTRM-2P-2S1D': if 'st' in insn_name and 'x' not in insn_name: # stwu/stbu etc res['Etype'] = 'EXTRA2' # RM EXTRA2 type