From: lkcl Date: Fri, 2 Jun 2023 23:39:47 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56eb077c9326e37034c1c9b11809ea01fb18d6a5;p=libreriscv.git --- diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 16a3d9660..8d732f474 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -65,18 +65,11 @@ considered an independent "Defined Word-instruction"[^dwi] that augments the beh the following instruction (also a Defined Word-instruction), but does **not** change the actual Decoding of that following instruction just because it is Prefixed. Unlike EXT100-163, where the Suffix is considered an entirely new Opcode Space, -SVP64-Prefixed instructions **MUST NEVER** be treated or regarded +SVP64-Prefixed instructions must never be treated or regarded as a different Opcode Space. [^dwi]: Defined Word-instruction: Power ISA v3.1 Section 1.6 -*Architectural note: Treating the SVP64 Prefix as an "Independent" 64-bit Encoding Space and attempting -to allocate non-Orthogonal Opcodes within it will result -in catastrophic unviability of Simple-V. The Orthogonality of the Scalar vs Prefixed-Scalar -spaces has to be considered inviolate, to the extent that even RESERVED spaces must be -kept identical. The complexity at the Decode Phase by violating the RISC paradigm inherent -in Simple-V will be unimplementable* - Two apparent exceptions to the above hard rule exist: SV Branch-Conditional operations and LD/ST-update "Post-Increment" Mode. Post-Increment was considered sufficiently high priority @@ -100,7 +93,8 @@ greatly complexifying Parallel Instruction-Length Detection. Therefore it has to be prohibited to accept RFCs which fundamentally violate the following hard requirement: **under no circumstances** must the use of SVP64 24-bit Suffixes **also** imply a different Opcode space -from **any** non-prefixed Word, even RESERVED or Illegal Words.* +from **any** non-prefixed Word. Even RESERVED or Illegal Words must be +Orthogonal.* Subset implementations in hardware are permitted, as long as certain rules are followed, allowing for full soft-emulation including future