From: Tim 'mithro' Ansell <mithro@mithis.com>
Date: Sun, 29 Oct 2017 18:11:53 +0000 (-0700)
Subject: Make the interrupt dicts read only.
X-Git-Tag: 24jan2021_ls180~1799^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=56ef22902926e5edfdb524a064804823fe449502;p=litex.git

Make the interrupt dicts read only.
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index f899bac4..6274216a 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -25,6 +25,19 @@ def mem_decoder(address, start=26, end=29):
     return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
 
 
+class ReadOnlyDict(dict):
+    def __readonly__(self, *args, **kwargs):
+        raise RuntimeError("Cannot modify ReadOnlyDict")
+    __setitem__ = __readonly__
+    __delitem__ = __readonly__
+    pop = __readonly__
+    popitem = __readonly__
+    clear = __readonly__
+    update = __readonly__
+    setdefault = __readonly__
+    del __readonly__
+
+
 class SoCCore(Module):
     csr_map = {
         "crg":            0,  # user
@@ -161,8 +174,11 @@ class SoCCore(Module):
         # Make sure other functions are not using this value.
         self.soc_interrupt_map = None
 
+        # Make the interrupt vector read only
+        self.interrupt_map = ReadOnlyDict(self.interrupt_map)
+
         # Save the interrupt reverse map
-        self.interrupt_rmap = interrupt_rmap
+        self.interrupt_rmap = ReadOnlyDict(interrupt_rmap)
 
 
     def add_cpu_or_bridge(self, cpu_or_bridge):