From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Dec 2021 04:53:45 +0000 (+0000)
Subject: mmu.py comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5701a3e5f35ffde6aca665850336f76389efd4f9;p=soc.git

mmu.py comments
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index c70ba8c4..376f8405 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -326,13 +326,14 @@ class MMU(Elaboratable):
             with m.If(leaf):
                 # check permissions and RC bits
                 with m.If(r.priv | ~eaa[EAA_PRIV]):
-                    with m.If(~r.iside):
-                        comb += perm_ok.eq(eaa[EAA_WR] | 
-                                          (eaa[EAA_RD] & ~r.store))
-                    with m.Else():
+                    with m.If(r.iside): # instruction-side request
                         # no IAMR, so no KUEP support for now
                         # deny execute permission if cache inhibited
                         comb += perm_ok.eq(eaa[EAA_EXE] & ~rpte.att[1])
+                    with m.Else():
+                        # Load/Store (read/write)
+                        comb += perm_ok.eq(eaa[EAA_WR] |
+                                          (eaa[EAA_RD] & ~r.store))
                 comb += rc_ok.eq(rpte.r & (rpte.c | ~r.store))
 
                 # permissions / rc ok, load TLB, otherwise report error