From: Nicolai Hähnle Date: Thu, 2 Feb 2017 20:11:05 +0000 (+0100) Subject: radeonsi: enable ARB_sparse_buffer X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=570e50af4ba9f7e003465b4e91e2cb93ae1615a1;p=mesa.git radeonsi: enable ARB_sparse_buffer v2: - fill in DRM version requirement - disable on SI due to CP DMA faults Reviewed-by: Marek Olšák --- diff --git a/docs/features.txt b/docs/features.txt index 1e145e1ddad..6513c693fa0 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -298,7 +298,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve GL_ARB_shader_group_vote DONE (nvc0, radeonsi) GL_ARB_shader_stencil_export DONE (i965/gen9+, radeonsi, softpipe, llvmpipe, swr) GL_ARB_shader_viewport_layer_array DONE (i965/gen6+) - GL_ARB_sparse_buffer not started + GL_ARB_sparse_buffer DONE (radeonsi/CIK+) GL_ARB_sparse_texture not started GL_ARB_sparse_texture2 not started GL_ARB_sparse_texture_clamp not started diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html index 917ee94b578..74e389cdfea 100644 --- a/docs/relnotes/17.1.0.html +++ b/docs/relnotes/17.1.0.html @@ -47,6 +47,7 @@ Note: some of the new features are only available with certain drivers.
  • GL_ARB_gpu_shader_int64 on i965/gen8+, nvc0, radeonsi, softpipe, llvmpipe
  • GL_ARB_shader_clock on radeonsi
  • GL_ARB_shader_group_vote on radeonsi
    • +
  • GL_ARB_sparse_buffer on radeonsi/CIK+
  • GL_ARB_transform_feedback2 on i965/gen6
  • GL_ARB_transform_feedback_overflow_query on i965/gen6+
  • GL_NV_fill_rectangle on nvc0
    • diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 7f6545ca4d4..e163d7bd38c 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -478,6 +478,16 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) (sscreen->b.info.drm_major == 2 && sscreen->b.info.drm_minor < 50); + case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: + /* Disable on SI due to VM faults in CP DMA. Enable once these + * faults are mitigated in software. + */ + if (sscreen->b.chip_class >= CIK && + sscreen->b.info.drm_major == 3 && + sscreen->b.info.drm_minor >= 13) + return RADEON_SPARSE_PAGE_SIZE; + return 0; + /* Unsupported features. */ case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: @@ -493,7 +503,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_MUL_ZERO_WINS: case PIPE_CAP_UMA: case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: - case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: return 0; case PIPE_CAP_QUERY_BUFFER_OBJECT: