From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Apr 2015 08:20:02 +0000 (+0200)
Subject: liteeth: pep8 (E302)
X-Git-Tag: 24jan2021_ls180~2372
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5720638d85e69a6a30f344464568545b49705a25;p=litex.git

liteeth: pep8 (E302)
---

diff --git a/misoclib/com/liteeth/common.py b/misoclib/com/liteeth/common.py
index 8643b3fc..c29beb55 100644
--- a/misoclib/com/liteeth/common.py
+++ b/misoclib/com/liteeth/common.py
@@ -18,6 +18,7 @@ eth_interpacket_gap = 12
 eth_preamble = 0xD555555555555555
 buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
 
+
 class HField():
     def __init__(self, byte, offset, width):
         self.byte = byte
@@ -115,6 +116,7 @@ etherbone_record_header = {
     "rcount":           HField( 3,  0, 8)
 }
 
+
 def reverse_bytes(v):
     n = math.ceil(flen(v)/8)
     r = []
@@ -122,6 +124,7 @@ def reverse_bytes(v):
         r.append(v[i*8:min((i+1)*8, flen(v))])
     return Cat(iter(r))
 
+
 # layouts
 def _layout_from_header(header):
     _layout = []
@@ -129,6 +132,7 @@ def _layout_from_header(header):
         _layout.append((k, v.width))
     return _layout
 
+
 def _remove_from_layout(layout, *args):
     r = []
     for f in layout:
@@ -140,6 +144,7 @@ def _remove_from_layout(layout, *args):
             r.append(f)
     return r
 
+
 def eth_phy_description(dw):
     payload_layout = [
         ("data", dw),
@@ -148,6 +153,7 @@ def eth_phy_description(dw):
     ]
     return EndpointDescription(payload_layout, packetized=True)
 
+
 def eth_mac_description(dw):
     payload_layout = _layout_from_header(mac_header) + [
         ("data", dw),
@@ -156,6 +162,7 @@ def eth_mac_description(dw):
     ]
     return EndpointDescription(payload_layout, packetized=True)
 
+
 def eth_arp_description(dw):
     param_layout = _layout_from_header(arp_header)
     payload_layout = [
@@ -173,6 +180,7 @@ arp_table_response_layout = [
     ("mac_address", 48)
 ]
 
+
 def eth_ipv4_description(dw):
     param_layout = _layout_from_header(ipv4_header)
     payload_layout = [
@@ -181,6 +189,7 @@ def eth_ipv4_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_ipv4_user_description(dw):
     param_layout = [
         ("length", 16),
@@ -193,6 +202,7 @@ def eth_ipv4_user_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def convert_ip(s):
     ip = 0
     for e in s.split("."):
@@ -200,6 +210,7 @@ def convert_ip(s):
         ip += int(e)
     return ip
 
+
 def eth_icmp_description(dw):
     param_layout = _layout_from_header(icmp_header)
     payload_layout = [
@@ -208,6 +219,7 @@ def eth_icmp_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_icmp_user_description(dw):
     param_layout = _layout_from_header(icmp_header) + [
         ("ip_address", 32),
@@ -219,6 +231,7 @@ def eth_icmp_user_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_udp_description(dw):
     param_layout = _layout_from_header(udp_header)
     payload_layout = [
@@ -227,6 +240,7 @@ def eth_udp_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_udp_user_description(dw):
     param_layout = [
         ("src_port", 16),
@@ -240,6 +254,7 @@ def eth_udp_user_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_etherbone_packet_description(dw):
     param_layout = _layout_from_header(etherbone_packet_header)
     payload_layout = [
@@ -248,6 +263,7 @@ def eth_etherbone_packet_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_etherbone_packet_user_description(dw):
     param_layout = _layout_from_header(etherbone_packet_header)
     param_layout = _remove_from_layout(param_layout, "magic", "portsize", "addrsize", "version")
@@ -258,6 +274,7 @@ def eth_etherbone_packet_user_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_etherbone_record_description(dw):
     param_layout = _layout_from_header(etherbone_record_header)
     payload_layout = [
@@ -266,6 +283,7 @@ def eth_etherbone_record_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_etherbone_mmap_description(dw):
     param_layout = [
         ("we", 1),
@@ -279,6 +297,7 @@ def eth_etherbone_mmap_description(dw):
     ]
     return EndpointDescription(payload_layout, param_layout, packetized=True)
 
+
 def eth_tty_description(dw):
     payload_layout = [("data", dw)]
     return EndpointDescription(payload_layout, packetized=False)
diff --git a/misoclib/com/liteeth/core/__init__.py b/misoclib/com/liteeth/core/__init__.py
index 7d14ec32..10bd2f90 100644
--- a/misoclib/com/liteeth/core/__init__.py
+++ b/misoclib/com/liteeth/core/__init__.py
@@ -6,6 +6,7 @@ from misoclib.com.liteeth.core.ip import LiteEthIP
 from misoclib.com.liteeth.core.udp import LiteEthUDP
 from misoclib.com.liteeth.core.icmp import LiteEthICMP
 
+
 class LiteEthIPCore(Module, AutoCSR):
     def __init__(self, phy, mac_address, ip_address, clk_freq):
         self.submodules.mac = LiteEthMAC(phy, 8, interface="crossbar", with_hw_preamble_crc=True)
@@ -13,6 +14,7 @@ class LiteEthIPCore(Module, AutoCSR):
         self.submodules.ip = LiteEthIP(self.mac, mac_address, ip_address, self.arp.table)
         self.submodules.icmp = LiteEthICMP(self.ip, ip_address)
 
+
 class LiteEthUDPIPCore(LiteEthIPCore):
     def __init__(self, phy, mac_address, ip_address, clk_freq):
         LiteEthIPCore.__init__(self, phy, mac_address, ip_address, clk_freq)
diff --git a/misoclib/com/liteeth/core/arp/__init__.py b/misoclib/com/liteeth/core/arp/__init__.py
index 6efb2390..50bd9a5b 100644
--- a/misoclib/com/liteeth/core/arp/__init__.py
+++ b/misoclib/com/liteeth/core/arp/__init__.py
@@ -10,6 +10,7 @@ _arp_table_layout = [
         ("mac_address", 48)
     ]
 
+
 class LiteEthARPPacketizer(LiteEthPacketizer):
     def __init__(self):
         LiteEthPacketizer.__init__(self,
@@ -18,6 +19,7 @@ class LiteEthARPPacketizer(LiteEthPacketizer):
             arp_header,
             arp_header_len)
 
+
 class LiteEthARPTX(Module):
     def __init__(self, mac_address, ip_address):
         self.sink = sink = Sink(_arp_table_layout)
@@ -72,6 +74,7 @@ class LiteEthARPTX(Module):
             )
         )
 
+
 class LiteEthARPDepacketizer(LiteEthDepacketizer):
     def __init__(self):
         LiteEthDepacketizer.__init__(self,
@@ -80,6 +83,7 @@ class LiteEthARPDepacketizer(LiteEthDepacketizer):
             arp_header,
             arp_header_len)
 
+
 class LiteEthARPRX(Module):
     def __init__(self, mac_address, ip_address):
         self.sink = sink = Sink(eth_mac_description(8))
@@ -131,6 +135,7 @@ class LiteEthARPRX(Module):
             )
         )
 
+
 class LiteEthARPTable(Module):
     def __init__(self, clk_freq, max_requests=8):
         self.sink = sink = Sink(_arp_table_layout)             # from arp_rx
@@ -247,6 +252,7 @@ class LiteEthARPTable(Module):
             )
         )
 
+
 class LiteEthARP(Module):
     def __init__(self, mac, mac_address, ip_address, clk_freq):
         self.submodules.tx = tx = LiteEthARPTX(mac_address, ip_address)
diff --git a/misoclib/com/liteeth/core/etherbone/__init__.py b/misoclib/com/liteeth/core/etherbone/__init__.py
index 95285425..4b622a73 100644
--- a/misoclib/com/liteeth/core/etherbone/__init__.py
+++ b/misoclib/com/liteeth/core/etherbone/__init__.py
@@ -7,6 +7,7 @@ from misoclib.com.liteeth.core.etherbone.probe import *
 from misoclib.com.liteeth.core.etherbone.record import *
 from misoclib.com.liteeth.core.etherbone.wishbone import *
 
+
 class LiteEthEtherbone(Module):
     def __init__(self, udp, udp_port):
         # decode/encode etherbone packets
diff --git a/misoclib/com/liteeth/core/etherbone/packet.py b/misoclib/com/liteeth/core/etherbone/packet.py
index 7db4b5ca..fa8d76a3 100644
--- a/misoclib/com/liteeth/core/etherbone/packet.py
+++ b/misoclib/com/liteeth/core/etherbone/packet.py
@@ -3,6 +3,7 @@ from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
 from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
 
+
 class LiteEthEtherbonePacketPacketizer(LiteEthPacketizer):
     def __init__(self):
         LiteEthPacketizer.__init__(self,
@@ -11,6 +12,7 @@ class LiteEthEtherbonePacketPacketizer(LiteEthPacketizer):
             etherbone_packet_header,
             etherbone_packet_header_len)
 
+
 class LiteEthEtherbonePacketTX(Module):
     def __init__(self, udp_port):
         self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
@@ -52,6 +54,7 @@ class LiteEthEtherbonePacketTX(Module):
             )
         )
 
+
 class LiteEthEtherbonePacketDepacketizer(LiteEthDepacketizer):
     def __init__(self):
         LiteEthDepacketizer.__init__(self,
@@ -60,6 +63,7 @@ class LiteEthEtherbonePacketDepacketizer(LiteEthDepacketizer):
             etherbone_packet_header,
             etherbone_packet_header_len)
 
+
 class LiteEthEtherbonePacketRX(Module):
     def __init__(self):
         self.sink = sink = Sink(eth_udp_user_description(32))
@@ -117,6 +121,7 @@ class LiteEthEtherbonePacketRX(Module):
             )
         )
 
+
 class LiteEthEtherbonePacket(Module):
     def __init__(self, udp, udp_port):
         self.submodules.tx = tx = LiteEthEtherbonePacketTX(udp_port)
diff --git a/misoclib/com/liteeth/core/etherbone/probe.py b/misoclib/com/liteeth/core/etherbone/probe.py
index cdc7b7e2..bc25fe37 100644
--- a/misoclib/com/liteeth/core/etherbone/probe.py
+++ b/misoclib/com/liteeth/core/etherbone/probe.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthEtherboneProbe(Module):
     def __init__(self):
         self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
diff --git a/misoclib/com/liteeth/core/etherbone/record.py b/misoclib/com/liteeth/core/etherbone/record.py
index 3e053a52..09f9b198 100644
--- a/misoclib/com/liteeth/core/etherbone/record.py
+++ b/misoclib/com/liteeth/core/etherbone/record.py
@@ -3,6 +3,7 @@ from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
 from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
 
+
 class LiteEthEtherboneRecordPacketizer(LiteEthPacketizer):
     def __init__(self):
         LiteEthPacketizer.__init__(self,
@@ -11,6 +12,7 @@ class LiteEthEtherboneRecordPacketizer(LiteEthPacketizer):
             etherbone_record_header,
             etherbone_record_header_len)
 
+
 class LiteEthEtherboneRecordDepacketizer(LiteEthDepacketizer):
     def __init__(self):
         LiteEthDepacketizer.__init__(self,
@@ -19,6 +21,7 @@ class LiteEthEtherboneRecordDepacketizer(LiteEthDepacketizer):
             etherbone_record_header,
             etherbone_record_header_len)
 
+
 class LiteEthEtherboneRecordReceiver(Module):
     def __init__(self, buffer_depth=256):
         self.sink = sink = Sink(eth_etherbone_record_description(32))
@@ -90,6 +93,7 @@ class LiteEthEtherboneRecordReceiver(Module):
             )
         )
 
+
 class LiteEthEtherboneRecordSender(Module):
     def __init__(self, buffer_depth=256):
         self.sink = sink = Sink(eth_etherbone_mmap_description(32))
@@ -138,6 +142,7 @@ class LiteEthEtherboneRecordSender(Module):
             )
         )
 
+
 # Limitation: For simplicity we only support 1 record per packet
 class LiteEthEtherboneRecord(Module):
     def __init__(self, endianness="big"):
diff --git a/misoclib/com/liteeth/core/etherbone/wishbone.py b/misoclib/com/liteeth/core/etherbone/wishbone.py
index 2cd3ac7a..d6d2b375 100644
--- a/misoclib/com/liteeth/core/etherbone/wishbone.py
+++ b/misoclib/com/liteeth/core/etherbone/wishbone.py
@@ -2,6 +2,7 @@ from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 from migen.bus import wishbone
 
+
 class LiteEthEtherboneWishboneMaster(Module):
     def __init__(self):
         self.sink = sink = Sink(eth_etherbone_mmap_description(32))
diff --git a/misoclib/com/liteeth/core/icmp/__init__.py b/misoclib/com/liteeth/core/icmp/__init__.py
index 66c2f6a4..720a377b 100644
--- a/misoclib/com/liteeth/core/icmp/__init__.py
+++ b/misoclib/com/liteeth/core/icmp/__init__.py
@@ -3,6 +3,7 @@ from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
 from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
 
+
 class LiteEthICMPPacketizer(LiteEthPacketizer):
     def __init__(self):
         LiteEthPacketizer.__init__(self,
@@ -11,6 +12,7 @@ class LiteEthICMPPacketizer(LiteEthPacketizer):
             icmp_header,
             icmp_header_len)
 
+
 class LiteEthICMPTX(Module):
     def __init__(self, ip_address):
         self.sink = sink = Sink(eth_icmp_user_description(8))
@@ -47,6 +49,7 @@ class LiteEthICMPTX(Module):
             )
         )
 
+
 class LiteEthICMPDepacketizer(LiteEthDepacketizer):
     def __init__(self):
         LiteEthDepacketizer.__init__(self,
@@ -55,6 +58,7 @@ class LiteEthICMPDepacketizer(LiteEthDepacketizer):
             icmp_header,
             icmp_header_len)
 
+
 class LiteEthICMPRX(Module):
     def __init__(self, ip_address):
         self.sink = sink = Sink(eth_ipv4_user_description(8))
@@ -109,6 +113,7 @@ class LiteEthICMPRX(Module):
             )
         )
 
+
 class LiteEthICMPEcho(Module):
     def __init__(self):
         self.sink = sink = Sink(eth_icmp_user_description(8))
@@ -122,6 +127,7 @@ class LiteEthICMPEcho(Module):
             self.source.checksum.eq(~((~self.buffer.source.checksum)-0x0800))
         ]
 
+
 class LiteEthICMP(Module):
     def __init__(self, ip, ip_address):
         self.submodules.tx = tx = LiteEthICMPTX(ip_address)
diff --git a/misoclib/com/liteeth/core/ip/__init__.py b/misoclib/com/liteeth/core/ip/__init__.py
index 9fb5a947..553f131c 100644
--- a/misoclib/com/liteeth/core/ip/__init__.py
+++ b/misoclib/com/liteeth/core/ip/__init__.py
@@ -5,6 +5,7 @@ from misoclib.com.liteeth.core.ip.crossbar import *
 from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
 from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
 
+
 class LiteEthIPV4Packetizer(LiteEthPacketizer):
     def __init__(self):
         LiteEthPacketizer.__init__(self,
@@ -13,6 +14,7 @@ class LiteEthIPV4Packetizer(LiteEthPacketizer):
             ipv4_header,
             ipv4_header_len)
 
+
 class LiteEthIPTX(Module):
     def __init__(self, mac_address, ip_address, arp_table):
         self.sink = sink = Sink(eth_ipv4_user_description(8))
@@ -92,6 +94,7 @@ class LiteEthIPTX(Module):
             )
         )
 
+
 class LiteEthIPV4Depacketizer(LiteEthDepacketizer):
     def __init__(self):
         LiteEthDepacketizer.__init__(self,
@@ -100,6 +103,7 @@ class LiteEthIPV4Depacketizer(LiteEthDepacketizer):
             ipv4_header,
             ipv4_header_len)
 
+
 class LiteEthIPRX(Module):
     def __init__(self, mac_address, ip_address):
         self.sink = sink = Sink(eth_mac_description(8))
@@ -164,6 +168,7 @@ class LiteEthIPRX(Module):
             )
         )
 
+
 class LiteEthIP(Module):
     def __init__(self, mac, mac_address, ip_address, arp_table):
         self.submodules.tx = tx = LiteEthIPTX(mac_address, ip_address, arp_table)
diff --git a/misoclib/com/liteeth/core/ip/checksum.py b/misoclib/com/liteeth/core/ip/checksum.py
index ea5e6156..24d13ce9 100644
--- a/misoclib/com/liteeth/core/ip/checksum.py
+++ b/misoclib/com/liteeth/core/ip/checksum.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthIPV4Checksum(Module):
     def __init__(self, words_per_clock_cycle=1, skip_checksum=False):
         self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog
diff --git a/misoclib/com/liteeth/core/ip/crossbar.py b/misoclib/com/liteeth/core/ip/crossbar.py
index 7b402e83..6228c9e7 100644
--- a/misoclib/com/liteeth/core/ip/crossbar.py
+++ b/misoclib/com/liteeth/core/ip/crossbar.py
@@ -2,22 +2,26 @@ from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar
 
+
 class LiteEthIPV4MasterPort:
     def __init__(self, dw):
         self.dw = dw
         self.source = Source(eth_ipv4_user_description(dw))
         self.sink = Sink(eth_ipv4_user_description(dw))
 
+
 class LiteEthIPV4SlavePort:
     def __init__(self, dw):
         self.dw = dw
         self.sink = Sink(eth_ipv4_user_description(dw))
         self.source = Source(eth_ipv4_user_description(dw))
 
+
 class LiteEthIPV4UserPort(LiteEthIPV4SlavePort):
     def __init__(self, dw):
         LiteEthIPV4SlavePort.__init__(self, dw)
 
+
 class LiteEthIPV4Crossbar(LiteEthCrossbar):
     def __init__(self):
         LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol")
diff --git a/misoclib/com/liteeth/core/tty/__init__.py b/misoclib/com/liteeth/core/tty/__init__.py
index 828d75b0..4a0917b3 100644
--- a/misoclib/com/liteeth/core/tty/__init__.py
+++ b/misoclib/com/liteeth/core/tty/__init__.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthTTYTX(Module):
     def __init__(self, ip_address, udp_port, fifo_depth=None):
         self.sink = sink = Sink(eth_tty_description(8))
@@ -58,6 +59,7 @@ class LiteEthTTYTX(Module):
                 )
             )
 
+
 class LiteEthTTYRX(Module):
     def __init__(self, ip_address, udp_port, fifo_depth=None):
         self.sink = sink = Sink(eth_udp_user_description(8))
@@ -83,6 +85,7 @@ class LiteEthTTYRX(Module):
                 Record.connect(fifo.source, source)
             ]
 
+
 class LiteEthTTY(Module):
     def __init__(self, udp, ip_address, udp_port,
             rx_fifo_depth=64,
diff --git a/misoclib/com/liteeth/core/udp/__init__.py b/misoclib/com/liteeth/core/udp/__init__.py
index 1518dec6..ec5ac2b7 100644
--- a/misoclib/com/liteeth/core/udp/__init__.py
+++ b/misoclib/com/liteeth/core/udp/__init__.py
@@ -4,6 +4,7 @@ from misoclib.com.liteeth.core.udp.crossbar import *
 from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
 from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
 
+
 class LiteEthUDPPacketizer(LiteEthPacketizer):
     def __init__(self):
         LiteEthPacketizer.__init__(self,
@@ -12,6 +13,7 @@ class LiteEthUDPPacketizer(LiteEthPacketizer):
             udp_header,
             udp_header_len)
 
+
 class LiteEthUDPTX(Module):
     def __init__(self, ip_address):
         self.sink = sink = Sink(eth_udp_user_description(8))
@@ -48,6 +50,7 @@ class LiteEthUDPTX(Module):
             )
         )
 
+
 class LiteEthUDPDepacketizer(LiteEthDepacketizer):
     def __init__(self):
         LiteEthDepacketizer.__init__(self,
@@ -56,6 +59,7 @@ class LiteEthUDPDepacketizer(LiteEthDepacketizer):
             udp_header,
             udp_header_len)
 
+
 class LiteEthUDPRX(Module):
     def __init__(self, ip_address):
         self.sink = sink = Sink(eth_ipv4_user_description(8))
@@ -109,6 +113,7 @@ class LiteEthUDPRX(Module):
             )
         )
 
+
 class LiteEthUDP(Module):
     def __init__(self, ip, ip_address):
         self.submodules.tx = tx = LiteEthUDPTX(ip_address)
diff --git a/misoclib/com/liteeth/core/udp/crossbar.py b/misoclib/com/liteeth/core/udp/crossbar.py
index 0bb55796..1ea2d037 100644
--- a/misoclib/com/liteeth/core/udp/crossbar.py
+++ b/misoclib/com/liteeth/core/udp/crossbar.py
@@ -3,22 +3,26 @@ from misoclib.com.liteeth.generic import *
 
 from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar
 
+
 class LiteEthUDPMasterPort:
     def __init__(self, dw):
         self.dw = dw
         self.source = Source(eth_udp_user_description(dw))
         self.sink = Sink(eth_udp_user_description(dw))
 
+
 class LiteEthUDPSlavePort:
     def __init__(self, dw):
         self.dw =dw
         self.sink = Sink(eth_udp_user_description(dw))
         self.source = Source(eth_udp_user_description(dw))
 
+
 class LiteEthUDPUserPort(LiteEthUDPSlavePort):
     def __init__(self, dw):
         LiteEthUDPSlavePort.__init__(self, dw)
 
+
 class LiteEthUDPCrossbar(LiteEthCrossbar):
     def __init__(self):
         LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port")
diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py
index 162ed184..4fdf983b 100644
--- a/misoclib/com/liteeth/example_designs/make.py
+++ b/misoclib/com/liteeth/example_designs/make.py
@@ -13,9 +13,11 @@ from mibuild.xilinx.common import *
 from misoclib.soc import cpuif
 from misoclib.com.liteeth.common import *
 
+
 def _import(default, name):
     return importlib.import_module(default + "." + name)
 
+
 def _get_args():
     parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
         description="""\
diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
index 1b32de0e..6f5f11d6 100644
--- a/misoclib/com/liteeth/example_designs/targets/base.py
+++ b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -13,6 +13,7 @@ from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
 from misoclib.com.liteeth.core import LiteEthUDPIPCore
 
+
 class BaseSoC(SoC, AutoCSR):
     csr_map = {
         "phy":        11,
@@ -42,6 +43,7 @@ class BaseSoC(SoC, AutoCSR):
         self.submodules.phy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
         self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)
 
+
 class BaseSoCDevel(BaseSoC, AutoCSR):
     csr_map = {
         "la":            20
diff --git a/misoclib/com/liteeth/example_designs/targets/etherbone.py b/misoclib/com/liteeth/example_designs/targets/etherbone.py
index 51f9cb9a..7e5d141b 100644
--- a/misoclib/com/liteeth/example_designs/targets/etherbone.py
+++ b/misoclib/com/liteeth/example_designs/targets/etherbone.py
@@ -8,6 +8,7 @@ from misoclib.com.liteeth.generic import *
 from targets.base import BaseSoC
 from misoclib.com.liteeth.core.etherbone import LiteEthEtherbone
 
+
 class EtherboneSoC(BaseSoC):
     default_platform = "kc705"
     def __init__(self, platform):
@@ -17,6 +18,7 @@ class EtherboneSoC(BaseSoC):
         self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
         self.add_wb_master(self.etherbone.master.bus)
 
+
 class EtherboneSoCDevel(EtherboneSoC):
     csr_map = {
         "la":            20
diff --git a/misoclib/com/liteeth/example_designs/targets/tty.py b/misoclib/com/liteeth/example_designs/targets/tty.py
index a4a6f749..a915c857 100644
--- a/misoclib/com/liteeth/example_designs/targets/tty.py
+++ b/misoclib/com/liteeth/example_designs/targets/tty.py
@@ -8,6 +8,7 @@ from misoclib.com.liteeth.generic import *
 from targets.base import BaseSoC
 from misoclib.com.liteeth.core.tty import LiteEthTTY
 
+
 class TTYSoC(BaseSoC):
     default_platform = "kc705"
     def __init__(self, platform):
@@ -17,6 +18,7 @@ class TTYSoC(BaseSoC):
         self.submodules.tty = LiteEthTTY(self.core.udp, convert_ip("192.168.0.14"), 10000)
         self.comb += Record.connect(self.tty.source, self.tty.sink)
 
+
 class TTYSoCDevel(TTYSoC):
     csr_map = {
         "la":            20
diff --git a/misoclib/com/liteeth/example_designs/targets/udp.py b/misoclib/com/liteeth/example_designs/targets/udp.py
index 746f1151..76f13990 100644
--- a/misoclib/com/liteeth/example_designs/targets/udp.py
+++ b/misoclib/com/liteeth/example_designs/targets/udp.py
@@ -7,6 +7,7 @@ from misoclib.com.liteeth.generic import *
 
 from targets.base import BaseSoC
 
+
 class UDPSoC(BaseSoC):
     default_platform = "kc705"
     def __init__(self, platform):
@@ -28,6 +29,7 @@ class UDPSoC(BaseSoC):
             setattr(self.submodules, name, buf)
         self.comb += Port.connect(port, buf)
 
+
 class UDPSoCDevel(UDPSoC):
     csr_map = {
         "la":            20
diff --git a/misoclib/com/liteeth/example_designs/test/make.py b/misoclib/com/liteeth/example_designs/test/make.py
index 1d3f2d9d..2c8bd783 100644
--- a/misoclib/com/liteeth/example_designs/test/make.py
+++ b/misoclib/com/liteeth/example_designs/test/make.py
@@ -1,6 +1,7 @@
 #!/usr/bin/env python3
 import argparse, importlib
 
+
 def _get_args():
     parser = argparse.ArgumentParser()
     parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
diff --git a/misoclib/com/liteeth/example_designs/test/test_etherbone.py b/misoclib/com/liteeth/example_designs/test/test_etherbone.py
index 715de265..d8eeef76 100644
--- a/misoclib/com/liteeth/example_designs/test/test_etherbone.py
+++ b/misoclib/com/liteeth/example_designs/test/test_etherbone.py
@@ -5,6 +5,7 @@ SRAM_BASE = 0x02000000
 
 import socket
 
+
 def main(wb):
     sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
 
diff --git a/misoclib/com/liteeth/example_designs/test/test_la.py b/misoclib/com/liteeth/example_designs/test/test_la.py
index 45686bba..1a4dc169 100644
--- a/misoclib/com/liteeth/example_designs/test/test_la.py
+++ b/misoclib/com/liteeth/example_designs/test/test_la.py
@@ -1,6 +1,7 @@
 import time
 from misoclib.tools.litescope.host.driver.la import LiteScopeLADriver
 
+
 def main(wb):
     la = LiteScopeLADriver(wb.regs, "la", debug=True)
 
diff --git a/misoclib/com/liteeth/example_designs/test/test_tty.py b/misoclib/com/liteeth/example_designs/test/test_tty.py
index a2a7aa92..fdf1d038 100644
--- a/misoclib/com/liteeth/example_designs/test/test_tty.py
+++ b/misoclib/com/liteeth/example_designs/test/test_tty.py
@@ -1,6 +1,7 @@
 import socket
 import threading
 
+
 def test(fpga_ip, udp_port, test_message):
     tx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
     rx_sock  = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
@@ -31,6 +32,7 @@ def test(fpga_ip, udp_port, test_message):
     except KeyboardInterrupt:
         pass
 
+
 def main(wb):
     test_message = "LiteEth virtual TTY Hello world\n"
     test("192.168.0.42", 10000, test_message)
diff --git a/misoclib/com/liteeth/example_designs/test/test_udp.py b/misoclib/com/liteeth/example_designs/test/test_udp.py
index 68e62c07..6b28974d 100644
--- a/misoclib/com/liteeth/example_designs/test/test_udp.py
+++ b/misoclib/com/liteeth/example_designs/test/test_udp.py
@@ -7,12 +7,14 @@ KB = 1024
 MB = 1024*KB
 GB = 1024*MB
 
+
 def seed_to_data(seed, random=True):
     if random:
         return (seed * 0x31415979 + 1) & 0xffffffff
     else:
         return seed
 
+
 def check(p1, p2):
     p1 = copy.deepcopy(p1)
     p2 = copy.deepcopy(p2)
@@ -34,6 +36,7 @@ def check(p1, p2):
                 errors += 1
         return shift, length, errors
 
+
 def generate_packet(seed, length):
     r = []
     for i in range(length):
@@ -41,6 +44,7 @@ def generate_packet(seed, length):
         seed += 1
     return r, seed
 
+
 def test(fpga_ip, udp_port, test_size):
     tx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
     rx_sock  = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
@@ -76,6 +80,7 @@ def test(fpga_ip, udp_port, test_size):
     except KeyboardInterrupt:
         pass
 
+
 def main(wb):
     test("192.168.0.42", 6000, 128*KB)
     test("192.168.0.42", 8000, 128*KB)
diff --git a/misoclib/com/liteeth/generic/__init__.py b/misoclib/com/liteeth/generic/__init__.py
index cebfe76b..cff32b0a 100644
--- a/misoclib/com/liteeth/generic/__init__.py
+++ b/misoclib/com/liteeth/generic/__init__.py
@@ -1,6 +1,7 @@
 from migen.fhdl.decorators import ModuleTransformer
 from misoclib.com.liteeth.common import *
 
+
 # Generic classes
 class Port:
     def connect(self, port):
@@ -10,6 +11,7 @@ class Port:
         ]
         return r
 
+
 # Generic modules
 class BufferizeEndpoints(ModuleTransformer):
     def __init__(self, *names):
@@ -40,6 +42,7 @@ class BufferizeEndpoints(ModuleTransformer):
             submodule.comb += Record.connect(source, buf.d)
             setattr(self, name, buf.q)
 
+
 class EndpointPacketStatus(Module):
     def __init__(self, endpoint):
         self.start = Signal()
@@ -59,6 +62,7 @@ class EndpointPacketStatus(Module):
             )
         self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
 
+
 class PacketBuffer(Module):
     def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
         self.sink = sink = Sink(description)
diff --git a/misoclib/com/liteeth/generic/arbiter.py b/misoclib/com/liteeth/generic/arbiter.py
index 07200a93..cb6503b0 100644
--- a/misoclib/com/liteeth/generic/arbiter.py
+++ b/misoclib/com/liteeth/generic/arbiter.py
@@ -2,6 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.roundrobin import *
 from migen.genlib.record import *
 
+
 class Arbiter(Module):
     def __init__(self, sources, sink):
         if len(sources) == 0:
diff --git a/misoclib/com/liteeth/generic/crossbar.py b/misoclib/com/liteeth/generic/crossbar.py
index 67268b41..9938df9f 100644
--- a/misoclib/com/liteeth/generic/crossbar.py
+++ b/misoclib/com/liteeth/generic/crossbar.py
@@ -5,6 +5,7 @@ from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.generic.arbiter import Arbiter
 from misoclib.com.liteeth.generic.dispatcher import Dispatcher
 
+
 class LiteEthCrossbar(Module):
     def __init__(self, master_port, dispatch_param):
         self.users = OrderedDict()
diff --git a/misoclib/com/liteeth/generic/depacketizer.py b/misoclib/com/liteeth/generic/depacketizer.py
index 2a0dc5eb..c6e13dff 100644
--- a/misoclib/com/liteeth/generic/depacketizer.py
+++ b/misoclib/com/liteeth/generic/depacketizer.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 def _decode_header(h_dict, h_signal, obj):
     r = []
     for k, v in sorted(h_dict.items()):
@@ -9,6 +10,7 @@ def _decode_header(h_dict, h_signal, obj):
         r.append(getattr(obj, k).eq(reverse_bytes(h_signal[start:end])))
     return r
 
+
 class LiteEthDepacketizer(Module):
     def __init__(self, sink_description, source_description, header_type, header_length):
         self.sink = sink = Sink(sink_description)
diff --git a/misoclib/com/liteeth/generic/dispatcher.py b/misoclib/com/liteeth/generic/dispatcher.py
index a822bded..3f88cff0 100644
--- a/misoclib/com/liteeth/generic/dispatcher.py
+++ b/misoclib/com/liteeth/generic/dispatcher.py
@@ -1,6 +1,7 @@
 from migen.fhdl.std import *
 from migen.genlib.record import *
 
+
 class Dispatcher(Module):
     def __init__(self, source, sinks, one_hot=False):
         if len(sinks) == 0:
diff --git a/misoclib/com/liteeth/generic/packetizer.py b/misoclib/com/liteeth/generic/packetizer.py
index 7412d965..8ad2bf15 100644
--- a/misoclib/com/liteeth/generic/packetizer.py
+++ b/misoclib/com/liteeth/generic/packetizer.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 def _encode_header(h_dict, h_signal, obj):
     r = []
     for k, v in sorted(h_dict.items()):
@@ -9,6 +10,7 @@ def _encode_header(h_dict, h_signal, obj):
         r.append(h_signal[start:end].eq(reverse_bytes(getattr(obj, k))))
     return r
 
+
 class LiteEthPacketizer(Module):
     def __init__(self, sink_description, source_description, header_type, header_length):
         self.sink = sink = Sink(sink_description)
diff --git a/misoclib/com/liteeth/mac/__init__.py b/misoclib/com/liteeth/mac/__init__.py
index 9ac65314..7611f192 100644
--- a/misoclib/com/liteeth/mac/__init__.py
+++ b/misoclib/com/liteeth/mac/__init__.py
@@ -4,6 +4,7 @@ from misoclib.com.liteeth.mac.common import *
 from misoclib.com.liteeth.mac.core import LiteEthMACCore
 from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface
 
+
 class LiteEthMAC(Module, AutoCSR):
     def __init__(self, phy, dw, interface="crossbar", endianness="big",
             with_hw_preamble_crc=True):
diff --git a/misoclib/com/liteeth/mac/common.py b/misoclib/com/liteeth/mac/common.py
index 7e6aadb6..d5a6d579 100644
--- a/misoclib/com/liteeth/mac/common.py
+++ b/misoclib/com/liteeth/mac/common.py
@@ -4,6 +4,7 @@ from misoclib.com.liteeth.generic.depacketizer import LiteEthDepacketizer
 from misoclib.com.liteeth.generic.packetizer import LiteEthPacketizer
 from misoclib.com.liteeth.generic.crossbar import LiteEthCrossbar
 
+
 class LiteEthMACDepacketizer(LiteEthDepacketizer):
     def __init__(self):
         LiteEthDepacketizer.__init__(self,
@@ -12,6 +13,7 @@ class LiteEthMACDepacketizer(LiteEthDepacketizer):
             mac_header,
             mac_header_len)
 
+
 class LiteEthMACPacketizer(LiteEthPacketizer):
     def __init__(self):
         LiteEthPacketizer.__init__(self,
@@ -20,20 +22,24 @@ class LiteEthMACPacketizer(LiteEthPacketizer):
             mac_header,
             mac_header_len)
 
+
 class LiteEthMACMasterPort:
     def __init__(self, dw):
         self.source = Source(eth_mac_description(dw))
         self.sink = Sink(eth_mac_description(dw))
 
+
 class LiteEthMACSlavePort:
     def __init__(self, dw):
         self.sink = Sink(eth_mac_description(dw))
         self.source = Source(eth_mac_description(dw))
 
+
 class LiteEthMACUserPort(LiteEthMACSlavePort):
     def __init__(self, dw):
         LiteEthMACSlavePort.__init__(self, dw)
 
+
 class LiteEthMACCrossbar(LiteEthCrossbar):
     def __init__(self):
         LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type")
diff --git a/misoclib/com/liteeth/mac/core/__init__.py b/misoclib/com/liteeth/mac/core/__init__.py
index 4aebf81b..da512aee 100644
--- a/misoclib/com/liteeth/mac/core/__init__.py
+++ b/misoclib/com/liteeth/mac/core/__init__.py
@@ -3,6 +3,7 @@ from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be
 from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
 
+
 class LiteEthMACCore(Module, AutoCSR):
     def __init__(self, phy, dw, endianness="big",
             with_preamble_crc=True,
diff --git a/misoclib/com/liteeth/mac/core/crc.py b/misoclib/com/liteeth/mac/core/crc.py
index b272ca19..5f0996ab 100644
--- a/misoclib/com/liteeth/mac/core/crc.py
+++ b/misoclib/com/liteeth/mac/core/crc.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthMACCRCEngine(Module):
     """Cyclic Redundancy Check Engine
 
@@ -69,6 +70,7 @@ class LiteEthMACCRCEngine(Module):
                     xors += [self.data[n]]
             self.comb += self.next[i].eq(optree("^", xors))
 
+
 @DecorateModule(InsertReset)
 @DecorateModule(InsertCE)
 class LiteEthMACCRC32(Module):
@@ -112,6 +114,7 @@ class LiteEthMACCRC32(Module):
             self.error.eq(self.engine.next != self.check)
         ]
 
+
 class LiteEthMACCRCInserter(Module):
     """CRC Inserter
 
@@ -186,10 +189,12 @@ class LiteEthMACCRCInserter(Module):
             )
         self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
 
+
 class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter):
     def __init__(self, description):
         LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, description)
 
+
 class LiteEthMACCRCChecker(Module):
     """CRC Checker
 
@@ -272,6 +277,7 @@ class LiteEthMACCRCChecker(Module):
         )
         self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
 
+
 class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):
     def __init__(self, description):
         LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, description)
diff --git a/misoclib/com/liteeth/mac/core/gap.py b/misoclib/com/liteeth/mac/core/gap.py
index b814ed8f..07620113 100644
--- a/misoclib/com/liteeth/mac/core/gap.py
+++ b/misoclib/com/liteeth/mac/core/gap.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthMACGap(Module):
     def __init__(self, dw, ack_on_gap=False):
         self.sink = sink = Sink(eth_phy_description(dw))
diff --git a/misoclib/com/liteeth/mac/core/last_be.py b/misoclib/com/liteeth/mac/core/last_be.py
index c14177d6..200c2cd2 100644
--- a/misoclib/com/liteeth/mac/core/last_be.py
+++ b/misoclib/com/liteeth/mac/core/last_be.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthMACTXLastBE(Module):
     def __init__(self, dw):
         self.sink = sink = Sink(eth_phy_description(dw))
@@ -23,6 +24,7 @@ class LiteEthMACTXLastBE(Module):
             sink.ack.eq(source.ack)
         ]
 
+
 class LiteEthMACRXLastBE(Module):
     def __init__(self, dw):
         self.sink = sink = Sink(eth_phy_description(dw))
diff --git a/misoclib/com/liteeth/mac/core/padding.py b/misoclib/com/liteeth/mac/core/padding.py
index 4bc02cca..54003288 100644
--- a/misoclib/com/liteeth/mac/core/padding.py
+++ b/misoclib/com/liteeth/mac/core/padding.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthMACPaddingInserter(Module):
     def __init__(self, dw, packet_min_length):
         self.sink = sink = Sink(eth_phy_description(dw))
@@ -36,6 +37,7 @@ class LiteEthMACPaddingInserter(Module):
             )
         )
 
+
 class LiteEthMACPaddingChecker(Module):
     def __init__(self, dw, packet_min_length):
         self.sink = sink = Sink(eth_phy_description(dw))
diff --git a/misoclib/com/liteeth/mac/core/preamble.py b/misoclib/com/liteeth/mac/core/preamble.py
index 8ddc0e93..3394e0e8 100644
--- a/misoclib/com/liteeth/mac/core/preamble.py
+++ b/misoclib/com/liteeth/mac/core/preamble.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthMACPreambleInserter(Module):
     def __init__(self, dw):
         self.sink = Sink(eth_phy_description(dw))
@@ -50,6 +51,7 @@ class LiteEthMACPreambleInserter(Module):
             )
         )
 
+
 class LiteEthMACPreambleChecker(Module):
     def __init__(self, dw):
         self.sink = Sink(eth_phy_description(dw))
diff --git a/misoclib/com/liteeth/mac/frontend/sram.py b/misoclib/com/liteeth/mac/frontend/sram.py
index 724509cc..f5f1168c 100644
--- a/misoclib/com/liteeth/mac/frontend/sram.py
+++ b/misoclib/com/liteeth/mac/frontend/sram.py
@@ -4,6 +4,7 @@ from misoclib.com.liteeth.generic import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 
+
 class LiteEthMACSRAMWriter(Module, AutoCSR):
     def __init__(self, dw, depth, nslots=2):
         self.sink = sink = Sink(eth_phy_description(dw))
@@ -225,6 +226,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
             cases[n] = [source.data.eq(port.dat_r)]
         self.comb += Case(rd_slot, cases)
 
+
 class LiteEthMACSRAM(Module, AutoCSR):
     def __init__(self, dw, depth, nrxslots, ntxslots):
         self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots)
diff --git a/misoclib/com/liteeth/mac/frontend/wishbone.py b/misoclib/com/liteeth/mac/frontend/wishbone.py
index 240df40e..05347806 100644
--- a/misoclib/com/liteeth/mac/frontend/wishbone.py
+++ b/misoclib/com/liteeth/mac/frontend/wishbone.py
@@ -5,6 +5,7 @@ from misoclib.com.liteeth.mac.frontend import sram
 from migen.bus import wishbone
 from migen.fhdl.simplify import FullMemoryWE
 
+
 class LiteEthMACWishboneInterface(Module, AutoCSR):
     def __init__(self, dw, nrxslots=2, ntxslots=2):
         self.sink = Sink(eth_phy_description(dw))
diff --git a/misoclib/com/liteeth/phy/__init__.py b/misoclib/com/liteeth/phy/__init__.py
index 533fbd05..d06352ac 100644
--- a/misoclib/com/liteeth/phy/__init__.py
+++ b/misoclib/com/liteeth/phy/__init__.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 def LiteEthPHY(clock_pads, pads, **kwargs):
     # Autodetect PHY
     if hasattr(pads, "source_stb"):
diff --git a/misoclib/com/liteeth/phy/gmii.py b/misoclib/com/liteeth/phy/gmii.py
index c1712b97..a39453b4 100644
--- a/misoclib/com/liteeth/phy/gmii.py
+++ b/misoclib/com/liteeth/phy/gmii.py
@@ -3,6 +3,7 @@ from migen.genlib.io import DDROutput
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthPHYGMIITX(Module):
     def __init__(self, pads, pads_register):
         self.sink = sink = Sink(eth_phy_description(8))
@@ -19,6 +20,7 @@ class LiteEthPHYGMIITX(Module):
             self.comb += pads_eq
         self.comb += sink.ack.eq(1)
 
+
 class LiteEthPHYGMIIRX(Module):
     def __init__(self, pads):
         self.source = source = Source(eth_phy_description(8))
@@ -39,6 +41,7 @@ class LiteEthPHYGMIIRX(Module):
         ]
         self.comb += source.eop.eq(eop)
 
+
 class LiteEthPHYGMIICRG(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
         self._reset = CSRStorage()
@@ -76,6 +79,7 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
             AsyncResetSynchronizer(self.cd_eth_rx, reset),
         ]
 
+
 class LiteEthPHYGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
diff --git a/misoclib/com/liteeth/phy/gmii_mii.py b/misoclib/com/liteeth/phy/gmii_mii.py
index 2f5ac7b9..3c65168b 100644
--- a/misoclib/com/liteeth/phy/gmii_mii.py
+++ b/misoclib/com/liteeth/phy/gmii_mii.py
@@ -17,6 +17,7 @@ modes = {
 tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
 rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)]
 
+
 class LiteEthPHYGMIIMIITX(Module):
     def __init__(self, pads, mode):
         self.sink = sink = Sink(eth_phy_description(8))
@@ -50,6 +51,7 @@ class LiteEthPHYGMIIMIITX(Module):
             )
         ]
 
+
 class LiteEthPHYGMIIMIIRX(Module):
     def __init__(self, pads, mode):
         self.source = source = Source(eth_phy_description(8))
@@ -75,6 +77,7 @@ class LiteEthPHYGMIIMIIRX(Module):
             Record.connect(mux.source, source)
         ]
 
+
 class LiteEthGMIIMIIClockCounter(Module, AutoCSR):
     def __init__(self):
         self._reset = CSRStorage()
@@ -88,6 +91,7 @@ class LiteEthGMIIMIIClockCounter(Module, AutoCSR):
         ]
         self.specials += MultiReg(counter.value, self._value.status)
 
+
 class LiteEthPHYGMIIMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
diff --git a/misoclib/com/liteeth/phy/loopback.py b/misoclib/com/liteeth/phy/loopback.py
index 9658c5a5..aa046224 100644
--- a/misoclib/com/liteeth/phy/loopback.py
+++ b/misoclib/com/liteeth/phy/loopback.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthPHYLoopbackCRG(Module, AutoCSR):
     def __init__(self):
         self._reset = CSRStorage()
@@ -18,6 +19,7 @@ class LiteEthPHYLoopbackCRG(Module, AutoCSR):
             self.cd_eth_tx.rst.eq(reset)
         ]
 
+
 class LiteEthPHYLoopback(Module, AutoCSR):
     def __init__(self):
         self.dw = 8
diff --git a/misoclib/com/liteeth/phy/mii.py b/misoclib/com/liteeth/phy/mii.py
index cd6ba499..8c5659f2 100644
--- a/misoclib/com/liteeth/phy/mii.py
+++ b/misoclib/com/liteeth/phy/mii.py
@@ -1,10 +1,12 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 def converter_description(dw):
     payload_layout = [("data", dw)]
     return EndpointDescription(payload_layout, packetized=True)
 
+
 class LiteEthPHYMIITX(Module):
     def __init__(self, pads, pads_register=True):
         self.sink = sink = Sink(eth_phy_description(8))
@@ -28,6 +30,7 @@ class LiteEthPHYMIITX(Module):
         else:
             self.comb += pads_eq
 
+
 class LiteEthPHYMIIRX(Module):
     def __init__(self, pads):
         self.source = source = Source(eth_phy_description(8))
@@ -52,6 +55,7 @@ class LiteEthPHYMIIRX(Module):
         ]
         self.comb += Record.connect(converter.source, source)
 
+
 class LiteEthPHYMIICRG(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset):
         self._reset = CSRStorage()
@@ -81,6 +85,7 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
             AsyncResetSynchronizer(self.cd_eth_rx, reset),
         ]
 
+
 class LiteEthPHYMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
diff --git a/misoclib/com/liteeth/phy/sim.py b/misoclib/com/liteeth/phy/sim.py
index c3f08832..3c8268ff 100644
--- a/misoclib/com/liteeth/phy/sim.py
+++ b/misoclib/com/liteeth/phy/sim.py
@@ -3,6 +3,7 @@ import os
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
+
 class LiteEthPHYSimCRG(Module, AutoCSR):
     def __init__(self):
         self._reset = CSRStorage()
@@ -22,6 +23,7 @@ class LiteEthPHYSimCRG(Module, AutoCSR):
             self.cd_eth_tx.rst.eq(reset)
         ]
 
+
 class LiteEthPHYSim(Module, AutoCSR):
     def __init__(self, pads, tap="tap0", ip_address="192.168.0.14"):
         self.dw = 8
diff --git a/misoclib/com/liteeth/test/arp_tb.py b/misoclib/com/liteeth/test/arp_tb.py
index f2dedfd6..f7b76855 100644
--- a/misoclib/com/liteeth/test/arp_tb.py
+++ b/misoclib/com/liteeth/test/arp_tb.py
@@ -13,6 +13,7 @@ from misoclib.com.liteeth.test.model import phy, mac, arp
 ip_address = 0x12345678
 mac_address = 0x12345678abcd
 
+
 class TB(Module):
     def __init__(self):
         self.submodules.phy_model = phy.PHY(8, debug=False)
diff --git a/misoclib/com/liteeth/test/common.py b/misoclib/com/liteeth/test/common.py
index fb427309..0b26c4b2 100644
--- a/misoclib/com/liteeth/test/common.py
+++ b/misoclib/com/liteeth/test/common.py
@@ -6,6 +6,7 @@ from migen.genlib.record import *
 
 from misoclib.com.liteeth.common import *
 
+
 def print_with_prefix(s, prefix=""):
     if not isinstance(s, str):
         s = s.__repr__()
@@ -13,12 +14,14 @@ def print_with_prefix(s, prefix=""):
     for l in s:
         print(prefix + l)
 
+
 def seed_to_data(seed, random=True):
     if random:
         return (seed * 0x31415979 + 1) & 0xffffffff
     else:
         return seed
 
+
 def split_bytes(v, n, endianness="big"):
     r = []
     r_bytes = v.to_bytes(n, byteorder=endianness)
@@ -26,13 +29,16 @@ def split_bytes(v, n, endianness="big"):
         r.append(int(byte))
     return r
 
+
 def merge_bytes(b, endianness="big"):
     return int.from_bytes(bytes(b), endianness)
 
+
 def get_field_data(field, datas):
     v = merge_bytes(datas[field.byte:field.byte+math.ceil(field.width/8)])
     return (v >> field.offset) & (2**field.width-1)
 
+
 def comp(p1, p2):
     r = True
     for x, y in zip(p1, p2):
@@ -40,6 +46,7 @@ def comp(p1, p2):
             r = False
     return r
 
+
 def check(p1, p2):
     p1 = copy.deepcopy(p1)
     p2 = copy.deepcopy(p2)
@@ -61,9 +68,11 @@ def check(p1, p2):
                 errors += 1
         return shift, length, errors
 
+
 def randn(max_n):
     return random.randint(0, max_n-1)
 
+
 class Packet(list):
     def __init__(self, init=[]):
         self.ongoing = False
@@ -71,6 +80,7 @@ class Packet(list):
         for data in init:
             self.append(data)
 
+
 class PacketStreamer(Module):
     def __init__(self, description, last_be=None):
         self.source = Source(description)
@@ -115,6 +125,7 @@ class PacketStreamer(Module):
                 self.packet.done = True
                 selfp.source.stb = 0
 
+
 class PacketLogger(Module):
     def __init__(self, description):
         self.sink = Sink(description)
@@ -136,6 +147,7 @@ class PacketLogger(Module):
         if selfp.sink.stb == 1 and selfp.sink.eop == 1:
             self.packet.done = True
 
+
 class AckRandomizer(Module):
     def __init__(self, description, level=0):
         self.level = level
diff --git a/misoclib/com/liteeth/test/etherbone_tb.py b/misoclib/com/liteeth/test/etherbone_tb.py
index 97531467..0bdc65f9 100644
--- a/misoclib/com/liteeth/test/etherbone_tb.py
+++ b/misoclib/com/liteeth/test/etherbone_tb.py
@@ -13,6 +13,7 @@ from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp, etherbone
 ip_address = 0x12345678
 mac_address = 0x12345678abcd
 
+
 class TB(Module):
     def __init__(self):
         self.submodules.phy_model = phy.PHY(8, debug=False)
diff --git a/misoclib/com/liteeth/test/icmp_tb.py b/misoclib/com/liteeth/test/icmp_tb.py
index bade68d6..58027171 100644
--- a/misoclib/com/liteeth/test/icmp_tb.py
+++ b/misoclib/com/liteeth/test/icmp_tb.py
@@ -16,6 +16,7 @@ from misoclib.com.liteeth.test.model import phy, mac, arp, ip, icmp
 ip_address = 0x12345678
 mac_address = 0x12345678abcd
 
+
 class TB(Module):
     def __init__(self):
         self.submodules.phy_model = phy.PHY(8, debug=True)
diff --git a/misoclib/com/liteeth/test/ip_tb.py b/misoclib/com/liteeth/test/ip_tb.py
index 7c581dd5..1275b590 100644
--- a/misoclib/com/liteeth/test/ip_tb.py
+++ b/misoclib/com/liteeth/test/ip_tb.py
@@ -12,6 +12,7 @@ from misoclib.com.liteeth.test.model import phy, mac, arp, ip
 ip_address = 0x12345678
 mac_address = 0x12345678abcd
 
+
 class TB(Module):
     def __init__(self):
         self.submodules.phy_model = phy.PHY(8, debug=False)
diff --git a/misoclib/com/liteeth/test/mac_core_tb.py b/misoclib/com/liteeth/test/mac_core_tb.py
index 2f0edb33..b49cbc1a 100644
--- a/misoclib/com/liteeth/test/mac_core_tb.py
+++ b/misoclib/com/liteeth/test/mac_core_tb.py
@@ -9,6 +9,7 @@ from misoclib.com.liteeth.mac.core import LiteEthMACCore
 from misoclib.com.liteeth.test.common import *
 from misoclib.com.liteeth.test.model import phy, mac
 
+
 class TB(Module):
     def __init__(self):
         self.submodules.phy_model = phy.PHY(8, debug=False)
diff --git a/misoclib/com/liteeth/test/mac_wishbone_tb.py b/misoclib/com/liteeth/test/mac_wishbone_tb.py
index e11d451b..f0e0f172 100644
--- a/misoclib/com/liteeth/test/mac_wishbone_tb.py
+++ b/misoclib/com/liteeth/test/mac_wishbone_tb.py
@@ -9,6 +9,7 @@ from misoclib.com.liteeth.mac import LiteEthMAC
 from misoclib.com.liteeth.test.common import *
 from misoclib.com.liteeth.test.model import phy, mac
 
+
 class WishboneMaster:
     def __init__(self, obj):
         self.obj = obj
@@ -41,6 +42,7 @@ class WishboneMaster:
         self.obj.stb = 0
         yield
 
+
 class SRAMReaderDriver:
     def __init__(self, obj):
         self.obj = obj
@@ -63,6 +65,7 @@ class SRAMReaderDriver:
         self.obj.ev.done.clear = 0
         yield
 
+
 class SRAMWriterDriver:
     def __init__(self, obj):
         self.obj = obj
@@ -77,6 +80,7 @@ class SRAMWriterDriver:
         self.obj.ev.available.clear = 0
         yield
 
+
 class TB(Module):
     def __init__(self):
         self.submodules.phy_model = phy.PHY(8, debug=False)
diff --git a/misoclib/com/liteeth/test/model/arp.py b/misoclib/com/liteeth/test/model/arp.py
index 52a12dfc..82a32b06 100644
--- a/misoclib/com/liteeth/test/model/arp.py
+++ b/misoclib/com/liteeth/test/model/arp.py
@@ -5,11 +5,13 @@ from misoclib.com.liteeth.test.common import *
 
 from misoclib.com.liteeth.test.model import mac
 
+
 def print_arp(s):
     print_with_prefix(s, "[ARP]")
 
 preamble = split_bytes(eth_preamble, 8)
 
+
 # ARP model
 class ARPPacket(Packet):
     def __init__(self, init=[]):
@@ -39,6 +41,7 @@ class ARPPacket(Packet):
             r += "{:02x}".format(d)
         return r
 
+
 class ARP(Module):
     def  __init__(self, mac, mac_address, ip_address, debug=False):
         self.mac = mac
diff --git a/misoclib/com/liteeth/test/model/dumps.py b/misoclib/com/liteeth/test/model/dumps.py
index 3ae38c26..91a61c67 100644
--- a/misoclib/com/liteeth/test/model/dumps.py
+++ b/misoclib/com/liteeth/test/model/dumps.py
@@ -1,8 +1,10 @@
 import re
 
+
 def format_dump(dump):
     return [int(s, 16) for s in re.split(r'[;,\s\n]\s*', dump) if s is not ""]
 
+
 def verify_packet(packet, infos):
     errors = 0
     for k, v in infos.items():
diff --git a/misoclib/com/liteeth/test/model/etherbone.py b/misoclib/com/liteeth/test/model/etherbone.py
index c2d875c8..0cf63614 100644
--- a/misoclib/com/liteeth/test/model/etherbone.py
+++ b/misoclib/com/liteeth/test/model/etherbone.py
@@ -5,9 +5,11 @@ from misoclib.com.liteeth.test.common import *
 
 from misoclib.com.liteeth.test.model import udp
 
+
 def print_etherbone(s):
     print_with_prefix(s, "[ETHERBONE]")
 
+
 # Etherbone model
 class EtherboneWrite:
     def __init__(self, data):
@@ -16,6 +18,7 @@ class EtherboneWrite:
     def __repr__(self):
         return "WR32 0x{:08x}".format(self.data)
 
+
 class EtherboneRead:
     def __init__(self, addr):
         self.addr = addr
@@ -23,6 +26,7 @@ class EtherboneRead:
     def __repr__(self):
         return "RD32 @ 0x{:08x}".format(self.addr)
 
+
 class EtherboneWrites(Packet):
     def __init__(self, init=[], base_addr=0, datas=[]):
         Packet.__init__(self, init)
@@ -74,6 +78,7 @@ class EtherboneWrites(Packet):
             r += write.__repr__() + "\n"
         return r
 
+
 class EtherboneReads(Packet):
     def __init__(self, init=[], base_ret_addr=0, addrs=[]):
         Packet.__init__(self, init)
@@ -125,6 +130,7 @@ class EtherboneReads(Packet):
             r += read.__repr__() + "\n"
         return r
 
+
 class EtherboneRecord(Packet):
     def __init__(self, init=[]):
         Packet.__init__(self, init)
@@ -208,6 +214,7 @@ class EtherboneRecord(Packet):
                 r += self.reads.__repr__()
         return r
 
+
 class EtherbonePacket(Packet):
     def __init__(self, init=[]):
         Packet.__init__(self, init)
@@ -275,6 +282,7 @@ class EtherbonePacket(Packet):
                 r += record.__repr__(i)
         return r
 
+
 class Etherbone(Module):
     def  __init__(self, udp, debug=False):
         self.udp = udp
diff --git a/misoclib/com/liteeth/test/model/icmp.py b/misoclib/com/liteeth/test/model/icmp.py
index 249b9fac..c89c244b 100644
--- a/misoclib/com/liteeth/test/model/icmp.py
+++ b/misoclib/com/liteeth/test/model/icmp.py
@@ -5,9 +5,11 @@ from misoclib.com.liteeth.test.common import *
 
 from misoclib.com.liteeth.test.model import ip
 
+
 def print_icmp(s):
     print_with_prefix(s, "[ICMP]")
 
+
 # ICMP model
 class ICMPPacket(Packet):
     def __init__(self, init=[]):
@@ -37,6 +39,7 @@ class ICMPPacket(Packet):
             r += "{:02x}".format(d)
         return r
 
+
 class ICMP(Module):
     def  __init__(self, ip, ip_address, debug=False):
         self.ip = ip
diff --git a/misoclib/com/liteeth/test/model/ip.py b/misoclib/com/liteeth/test/model/ip.py
index ee1bdbf6..165f1e0d 100644
--- a/misoclib/com/liteeth/test/model/ip.py
+++ b/misoclib/com/liteeth/test/model/ip.py
@@ -5,13 +5,16 @@ from misoclib.com.liteeth.test.common import *
 
 from misoclib.com.liteeth.test.model import mac
 
+
 def print_ip(s):
     print_with_prefix(s, "[IP]")
 
+
 def carry_around_add(a, b):
     c = a + b
     return (c & 0xffff) + (c >> 16)
 
+
 def checksum(msg):
     s = 0
     for i in range(0, len(msg), 2):
@@ -19,6 +22,7 @@ def checksum(msg):
         s = carry_around_add(s, w)
     return ~s & 0xffff
 
+
 # IP model
 class IPPacket(Packet):
     def __init__(self, init=[]):
@@ -61,6 +65,7 @@ class IPPacket(Packet):
             r += "{:02x}".format(d)
         return r
 
+
 class IP(Module):
     def  __init__(self, mac, mac_address, ip_address, debug=False, loopback=False):
         self.mac = mac
diff --git a/misoclib/com/liteeth/test/model/mac.py b/misoclib/com/liteeth/test/model/mac.py
index a3a7a8d5..6c06390d 100644
--- a/misoclib/com/liteeth/test/model/mac.py
+++ b/misoclib/com/liteeth/test/model/mac.py
@@ -3,11 +3,13 @@ import math, binascii
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.test.common import *
 
+
 def print_mac(s):
     print_with_prefix(s, "[MAC]")
 
 preamble = split_bytes(eth_preamble, 8, "little")
 
+
 def crc32(l):
     crc = []
     crc_bytes = split_bytes(binascii.crc32(bytes(l)), 4, "little")
@@ -15,6 +17,7 @@ def crc32(l):
         crc.append(int(byte))
     return crc
 
+
 # MAC model
 class MACPacket(Packet):
     def __init__(self, init=[]):
@@ -83,6 +86,7 @@ class MACPacket(Packet):
             r += "{:02x}".format(d)
         return r
 
+
 class MAC(Module):
     def  __init__(self, phy, debug=False, loopback=False):
         self.phy = phy
diff --git a/misoclib/com/liteeth/test/model/phy.py b/misoclib/com/liteeth/test/model/phy.py
index 5bb69731..0bc2908a 100644
--- a/misoclib/com/liteeth/test/model/phy.py
+++ b/misoclib/com/liteeth/test/model/phy.py
@@ -1,18 +1,22 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.test.common import *
 
+
 def print_phy(s):
     print_with_prefix(s, "[PHY]")
 
+
 # PHY model
 class PHYSource(PacketStreamer):
     def __init__(self, dw):
         PacketStreamer.__init__(self, eth_phy_description(dw))
 
+
 class PHYSink(PacketLogger):
     def __init__(self, dw):
         PacketLogger.__init__(self, eth_phy_description(dw))
 
+
 class PHY(Module):
     def __init__(self, dw, debug=False):
         self.dw = dw
diff --git a/misoclib/com/liteeth/test/model/udp.py b/misoclib/com/liteeth/test/model/udp.py
index f59ab116..c69b6c8c 100644
--- a/misoclib/com/liteeth/test/model/udp.py
+++ b/misoclib/com/liteeth/test/model/udp.py
@@ -5,9 +5,11 @@ from misoclib.com.liteeth.test.common import *
 
 from misoclib.com.liteeth.test.model import ip
 
+
 def print_udp(s):
     print_with_prefix(s, "[UDP]")
 
+
 # UDP model
 class UDPPacket(Packet):
     def __init__(self, init=[]):
@@ -37,6 +39,7 @@ class UDPPacket(Packet):
             r += "{:02x}".format(d)
         return r
 
+
 class UDP(Module):
     def  __init__(self, ip, ip_address, debug=False, loopback=False):
         self.ip = ip
diff --git a/misoclib/com/liteeth/test/udp_tb.py b/misoclib/com/liteeth/test/udp_tb.py
index 6803571a..00e1c789 100644
--- a/misoclib/com/liteeth/test/udp_tb.py
+++ b/misoclib/com/liteeth/test/udp_tb.py
@@ -12,6 +12,7 @@ from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp
 ip_address = 0x12345678
 mac_address = 0x12345678abcd
 
+
 class TB(Module):
     def __init__(self, dw=8):
         self.dw = dw