From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Wed, 19 Oct 2022 20:23:29 +0000 (+0300)
Subject: sv_binutils_fptrans: fix registers generation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5729ffc92471d016e96905b0ec054b19585f0760;p=openpower-isa.git

sv_binutils_fptrans: fix registers generation
---

diff --git a/src/openpower/sv/sv_binutils_fptrans.py b/src/openpower/sv/sv_binutils_fptrans.py
index d0e83460..d6aec3af 100644
--- a/src/openpower/sv/sv_binutils_fptrans.py
+++ b/src/openpower/sv/sv_binutils_fptrans.py
@@ -139,12 +139,16 @@ def asm(entry, binutils=False, regex=False):
     for (idx, operand) in enumerate(operands):
         values = []
         for each in operands:
-            if binutils and each.name in ("RT", "RA", "RB"):
+            if binutils and each.name in ("FRT", "FRA", "FRB"):
+                values.append("f0")
+            elif binutils and each.name in ("RT", "RA", "RB"):
                 values.append("r0")
             else:
                 values.append("0")
         value = str((1 << len(operand.span)) - 1)
-        if binutils and operand.name in ("RT", "RA", "RB"):
+        if binutils and operand.name in ("FRT", "FRA", "FRB"):
+            value = f"f{value}"
+        elif binutils and operand.name in ("RT", "RA", "RB"):
             value = f"r{value}"
         values[idx] = value
         sep = "\s+" if regex else " "