From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 5 Aug 2019 07:37:13 +0000 (+0100)
Subject: multiply mask width for concurrent pipeline
X-Git-Tag: ls180-24jan2020~547
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=573b5951047f068ac1f9fea79c7202a4fcfe4702;p=ieee754fpu.git

multiply mask width for concurrent pipeline
---

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 9bfcb49e..8b9e1086 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -177,7 +177,7 @@ class FPDIVMuxInOut(ReservationStations):
         cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix)
 
         self.pspec.pipekls = MaskCancellableRedir
-        self.pspec.maskwid = maskwid
+        self.pspec.maskwid = maskwid * num_rows # RS gets just maskwid
         self.pspec.fpformat = fmt
         self.pspec.n_comb_stages = n_comb_stages
         self.pspec.core_config = cfg