From: Will Schmidt <will_schmidt@vnet.ibm.com>
Date: Thu, 11 Oct 2018 20:59:15 +0000 (+0000)
Subject: fold-vec-mergeeo-floatdouble.c: New.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5746195cdc224e341c78aacd8360795b21459484;p=gcc.git

fold-vec-mergeeo-floatdouble.c: New.

[testsuite]

2018-10-09  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: New.
	* gcc.target/powerpc/fold-vec-mergeeo-int.c: New.
	* gcc.target/powerpc/fold-vec-mergeeo-longlong.c: New.

From-SVN: r265062
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3ee2817de00..3b19068fcd5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-11  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: New.
+	* gcc.target/powerpc/fold-vec-mergeeo-int.c: New.
+	* gcc.target/powerpc/fold-vec-mergeeo-longlong.c: New.
+
 2018-10-11  Tobias Burnus <burnus@net-b.de>
 
 	Revert:
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c
new file mode 100644
index 00000000000..5fe509a38ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_mergee and vec_mergeo
+ with float and double inputs produce the right codegen.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -mpower8-vector " } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+/*
+	vector float foo = vec_mergee (vector float, vector float);
+	vector float foo = vec_mergeo (vector float, vector float);
+	vector double foo = vec_mergee (vector double , vector double);
+	vector double foo = vec_mergeo (vector double , vector double);
+*/
+
+vector float
+testf_ee (vector float vf1, vector float vf2)
+{
+  return vec_mergee (vf1, vf2);
+}
+
+vector float
+testf_eo (vector float vf1, vector float vf2)
+{
+  return vec_mergeo (vf1, vf2);
+}
+
+vector double
+testd_ee ( vector double vd1, vector double vd2)
+{
+  return vec_mergee (vd1, vd2);
+}
+
+vector double
+testd_eo ( vector double vd1, vector double vd2)
+{
+  return vec_mergeo (vd1, vd2);
+}
+/* Doubles will generate vmrg*w instructions.  */
+/* { dg-final { scan-assembler-times "vmrgow" 1 } } */
+/* { dg-final { scan-assembler-times "vmrgew" 1 } } */
+/* Floats will generate some number of xxpermdi instructions.  Ensure we get at least one. */
+/* { dg-final { scan-assembler "xxpermdi" } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c
new file mode 100644
index 00000000000..bf171242964
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c
@@ -0,0 +1,48 @@
+/* Verify that overloaded built-ins for vec_mergee and vec_mergeo
+ with int inputs produce the right codegen.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector bool int
+testbi_ee (vector bool int v1, vector bool int v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector signed int
+testsi_ee (vector signed int v1, vector signed int v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector unsigned int
+testui_ee (vector unsigned int v1, vector unsigned int v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector bool int
+testbi_eo (vector bool int v1, vector bool int v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+vector signed int
+testsi_eo (vector signed int v1, vector signed int v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+vector unsigned int
+testui_eo (vector unsigned int v1, vector unsigned int v2)
+{
+  return vec_mergeo (v1, v2);
+}
+/* { dg-final { scan-assembler-times "vmrgew" 3 } } */
+/* { dg-final { scan-assembler-times "vmrgow" 3 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c
new file mode 100644
index 00000000000..c8317084bb8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c
@@ -0,0 +1,51 @@
+/* Verify that overloaded built-ins for vec_mergee and vec_mergeo
+ with long long inputs produce the right codegen.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector bool long long
+testbi_ee (vector bool long long v1, vector bool long long v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector bool long long
+testbi_eo (vector bool long long v1, vector bool long long v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+vector signed long long
+testsi_ee (vector signed long long v1, vector signed long long v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector signed long long
+testsi_eo (vector signed long long v1, vector signed long long v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+vector unsigned long long
+testui_ee (vector unsigned long long v1, vector unsigned long long v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector unsigned long long
+testui_eo (vector unsigned long long v1, vector unsigned long long v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+/* long long ...   */
+/* vec_mergee and vec_mergeo codegen will consist of some number of
+ xxpermdi instructions that will vary.  Ensure we get at least one. */
+/* { dg-final { scan-assembler "xxpermdi" } } */
+