From: Marek Olšák <marek.olsak@amd.com>
Date: Sun, 6 Sep 2015 13:43:23 +0000 (+0200)
Subject: radeonsi: remove TC L2 cache flush for index buffers on VI
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5749676d03d1a4964888a2d9a7624d3b96cc4886;p=mesa.git

radeonsi: remove TC L2 cache flush for index buffers on VI

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 43170ec446b..5face423941 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -813,9 +813,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		}
 	}
 
-	/* TODO: VI should read index buffers through TC, so this shouldn't be
-	 * needed on VI. */
-	if (info->indexed && r600_resource(ib.buffer)->TC_L2_dirty) {
+	/* VI reads index buffers through TC L2. */
+	if (info->indexed && sctx->b.chip_class <= CIK &&
+	    r600_resource(ib.buffer)->TC_L2_dirty) {
 		sctx->b.flags |= SI_CONTEXT_INV_TC_L2;
 		r600_resource(ib.buffer)->TC_L2_dirty = false;
 	}