From: Elie Tournier <tournier.elie@gmail.com>
Date: Thu, 16 Jul 2020 12:41:15 +0000 (+0100)
Subject: virgl: set PIPE_CAP_BLEND_EQUATION_ADVANCED
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=575ab303a80d02fb7eda451f636e013e2d95fa60;p=mesa.git

virgl: set PIPE_CAP_BLEND_EQUATION_ADVANCED

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5516>
---

diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c
index 3591762c9e3..348575d7b9f 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -262,6 +262,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_FBFETCH:
       return (vscreen->caps.caps.v2.capability_bits &
               VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
+   case PIPE_CAP_BLEND_EQUATION_ADVANCED:
+      return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_BLEND_EQUATION;
    case PIPE_CAP_TGSI_CLOCK:
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
    case PIPE_CAP_TGSI_ARRAY_COMPONENTS: