From: lkcl <lkcl@web>
Date: Thu, 24 Dec 2020 13:10:52 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~964
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5767af25e702adab0062e04a4c64f49896f949dc;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 3267fde40..d9e58ec5f 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -120,3 +120,6 @@ Sometimes with predication it is ok to leave the masked-out element alone (not m
         if (rs2.isvec)  { irs2 += 1; }
         if (id == VL or irs1 == VL or irs2 == VL)
            break
+
+Many Vector systems either have zeroing or they have nonzeroing, they do not have both.  This is because they usually have separate Vector register files. However SV sits on top of standard register files and consequently there are advantages to both, so both are provided.
+