From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 May 2019 14:44:24 +0000 (+0100)
Subject: relative imports
X-Git-Tag: ls180-24jan2020~1068
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=577b68586a746641ade96490af189687f98d2a46;p=ieee754fpu.git

relative imports
---

diff --git a/src/ieee754/add/test_fsm_experiment.py b/src/ieee754/add/test_fsm_experiment.py
index cfc401e8..eeff6f0a 100644
--- a/src/ieee754/add/test_fsm_experiment.py
+++ b/src/ieee754/add/test_fsm_experiment.py
@@ -10,7 +10,7 @@ from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
                                      FPOpOut, FPBase)
 from nmutil.nmoperator import eq
 from nmutil.singlepipe import SimpleHandshake, ControlBase
-from test_buf_pipe import data_chain2, Test5
+from nmutil.test.test_buf_pipe import data_chain2, Test5
 
 
 class FPDIV(FPBase, Elaboratable):
diff --git a/src/nmutil/test/test_buf_pipe.py b/src/nmutil/test/test_buf_pipe.py
index 089163c5..f9a4e50d 100644
--- a/src/nmutil/test/test_buf_pipe.py
+++ b/src/nmutil/test/test_buf_pipe.py
@@ -19,11 +19,11 @@ from nmigen.hdl.rec import Record
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
-from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
-from example_buf_pipe import ExampleStageCls
-from example_buf_pipe import PrevControl, NextControl, BufferedHandshake
-from example_buf_pipe import StageChain, ControlBase, StageCls
+from .example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
+from .example_buf_pipe import ExamplePipeline, UnbufferedPipeline
+from .example_buf_pipe import ExampleStageCls
+from .example_buf_pipe import PrevControl, NextControl, BufferedHandshake
+from .example_buf_pipe import StageChain, ControlBase, StageCls
 from nmutil.singlepipe import UnbufferedPipeline2
 from nmutil.singlepipe import SimpleHandshake
 from nmutil.singlepipe import PassThroughHandshake