From: Kevin Lim <ktlim@umich.edu>
Date: Sat, 4 Mar 2006 18:06:24 +0000 (-0500)
Subject: Merge ktlim@zizzer:/bk/m5
X-Git-Tag: m5_2.0_beta1~87^2~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5790e295a93e9aecd17696fc35106dccff094cfb;p=gem5.git

Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

arch/alpha/ev5.cc:
    Remove intr_post, it is no longer used.
arch/alpha/isa_traits.hh:
    Hand merge.

--HG--
extra : convert_revision : 94f14539a9e5646f8c368b15b2dff18ab2f492cf
---

5790e295a93e9aecd17696fc35106dccff094cfb
diff --cc arch/alpha/ev5.cc
index c6da628be,2cbfe7fd6..e313c1a1c
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@@ -163,33 -134,35 +134,6 @@@ AlphaISA::zeroRegisters(CPU *cpu
      cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
  }
  
--void
- AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 -ExecContext::ev5_temp_trap(Fault fault)
--{
- /*    bool use_pc = (fault == NoFault);
 -    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
 -    cpu->recordEvent(csprintf("Fault %s", fault->name()));
 -
 -    assert(!misspeculating());
 -    kernelStats->fault(fault);
--
--    if (fault->isA<ArithmeticFault>())
-         panic("arithmetic faults NYI...");
 -        panic("Arithmetic traps are unimplemented!");
--
-     // compute exception restart address
-     if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
-         // traps...  skip faulting instruction
-         regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
-     } else {
-         // fault, post fault at excepting instruction
-         regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
 -    // exception restart address
 -    if (!fault->isA<InterruptFault>() || !inPalMode())
 -        setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
 -
 -    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
 -        fault == InterruptFault && !inPalMode() */) {
 -        // traps...  skip faulting instruction.
 -        setMiscReg(AlphaISA::IPR_EXC_ADDR,
 -                   readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
--    }
--
-     // jump to expection address (PAL PC bit set here as well...)
-     if (!use_pc)
-         regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
-             (dynamic_cast<AlphaFault *>(fault.get()))->vect();
-     else
-         regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
- */
-     // that's it! (orders of magnitude less painful than x86)
 -    regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) +
 -        (dynamic_cast<AlphaFault *>(fault.get()))->vect();
 -    regs.npc = regs.pc + sizeof(MachInst);
--}
 -
--
  Fault
  ExecContext::hwrei()
  {
diff --cc arch/alpha/isa_traits.hh
index b8aeffdde,b1980b4b6..a551db485
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@@ -57,6 -57,8 +57,7 @@@ namespace AlphaIS
  {
  
      typedef uint32_t MachInst;
+     typedef uint64_t ExtMachInst;
 -//    typedef uint64_t Addr;
      typedef uint8_t  RegIndex;
  
      enum {