From: Gabe Black Date: Wed, 2 Mar 2011 07:18:47 +0000 (-0800) Subject: Spelling: Fix the a spelling error by changing mmaped to mmapped. X-Git-Tag: stable_2012_02_02~501 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=579c5f0b65290b46687273fc58bab5f6f2d17e07;p=gem5.git Spelling: Fix the a spelling error by changing mmaped to mmapped. There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. --HG-- rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh --- diff --git a/src/arch/SConscript b/src/arch/SConscript index 8c537182d..34367b274 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -50,7 +50,7 @@ isa_switch_hdrs = Split(''' kernel_stats.hh locked_mem.hh microcode_rom.hh - mmaped_ipr.hh + mmapped_ipr.hh mt.hh process.hh predecoder.hh diff --git a/src/arch/alpha/mmaped_ipr.hh b/src/arch/alpha/mmaped_ipr.hh deleted file mode 100644 index 99f8aeb06..000000000 --- a/src/arch/alpha/mmaped_ipr.hh +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -#ifndef __ARCH_ALPHA_MMAPED_IPR_HH__ -#define __ARCH_ALPHA_MMAPED_IPR_HH__ - -/** - * @file - * - * ISA-specific helper functions for memory mapped IPR accesses. - */ - -#include "base/types.hh" -#include "mem/packet.hh" - -class ThreadContext; - -namespace AlphaISA { - -inline Tick -handleIprRead(ThreadContext *xc, Packet *pkt) -{ - panic("No handleIprRead implementation in Alpha\n"); -} - - -inline Tick -handleIprWrite(ThreadContext *xc, Packet *pkt) -{ - panic("No handleIprWrite implementation in Alpha\n"); -} - - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_MMAPED_IPR_HH__ diff --git a/src/arch/alpha/mmapped_ipr.hh b/src/arch/alpha/mmapped_ipr.hh new file mode 100644 index 000000000..6c3403b33 --- /dev/null +++ b/src/arch/alpha/mmapped_ipr.hh @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __ARCH_ALPHA_MMAPPED_IPR_HH__ +#define __ARCH_ALPHA_MMAPPED_IPR_HH__ + +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "base/types.hh" +#include "mem/packet.hh" + +class ThreadContext; + +namespace AlphaISA { + +inline Tick +handleIprRead(ThreadContext *xc, Packet *pkt) +{ + panic("No handleIprRead implementation in Alpha\n"); +} + + +inline Tick +handleIprWrite(ThreadContext *xc, Packet *pkt) +{ + panic("No handleIprWrite implementation in Alpha\n"); +} + + +} // namespace AlphaISA + +#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__ diff --git a/src/arch/arm/mmaped_ipr.hh b/src/arch/arm/mmaped_ipr.hh deleted file mode 100644 index 8483ef7a2..000000000 --- a/src/arch/arm/mmaped_ipr.hh +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Stephen Hines - */ - -#ifndef __ARCH_ARM_MMAPED_IPR_HH__ -#define __ARCH_ARM_MMAPED_IPR_HH__ - -/** - * @file - * - * ISA-specific helper functions for memory mapped IPR accesses. - */ - -#include "base/misc.hh" -#include "mem/packet.hh" - -class ThreadContext; - -namespace ArmISA -{ -inline Tick -handleIprRead(ThreadContext *xc, Packet *pkt) -{ - panic("No implementation for handleIprRead in ARM\n"); -} - -inline Tick -handleIprWrite(ThreadContext *xc, Packet *pkt) -{ - panic("No implementation for handleIprWrite in ARM\n"); -} - - -} // namespace ArmISA - -#endif diff --git a/src/arch/arm/mmapped_ipr.hh b/src/arch/arm/mmapped_ipr.hh new file mode 100644 index 000000000..0f90ac35d --- /dev/null +++ b/src/arch/arm/mmapped_ipr.hh @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * Copyright (c) 2007-2008 The Florida State University + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Stephen Hines + */ + +#ifndef __ARCH_ARM_MMAPPED_IPR_HH__ +#define __ARCH_ARM_MMAPPED_IPR_HH__ + +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "base/misc.hh" +#include "mem/packet.hh" + +class ThreadContext; + +namespace ArmISA +{ +inline Tick +handleIprRead(ThreadContext *xc, Packet *pkt) +{ + panic("No implementation for handleIprRead in ARM\n"); +} + +inline Tick +handleIprWrite(ThreadContext *xc, Packet *pkt) +{ + panic("No implementation for handleIprWrite in ARM\n"); +} + + +} // namespace ArmISA + +#endif diff --git a/src/arch/mips/mmaped_ipr.hh b/src/arch/mips/mmaped_ipr.hh deleted file mode 100644 index 99c2e7fc7..000000000 --- a/src/arch/mips/mmaped_ipr.hh +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -#ifndef __ARCH_MIPS_MMAPED_IPR_HH__ -#define __ARCH_MIPS_MMAPED_IPR_HH__ - -/** - * @file - * - * ISA-specific helper functions for memory mapped IPR accesses. - */ - -#include "base/misc.hh" -#include "mem/packet.hh" - -class ThreadContext; - -namespace MipsISA -{ - -inline Tick -handleIprRead(ThreadContext *xc, Packet *pkt) -{ - panic("No implementation for handleIprRead in MIPS\n"); -} - -inline Tick -handleIprWrite(ThreadContext *xc, Packet *pkt) -{ - panic("No implementation for handleIprWrite in MIPS\n"); -} - -} // namespace MipsISA - -#endif diff --git a/src/arch/mips/mmapped_ipr.hh b/src/arch/mips/mmapped_ipr.hh new file mode 100644 index 000000000..14d6e3f42 --- /dev/null +++ b/src/arch/mips/mmapped_ipr.hh @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __ARCH_MIPS_MMAPPED_IPR_HH__ +#define __ARCH_MIPS_MMAPPED_IPR_HH__ + +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "base/misc.hh" +#include "mem/packet.hh" + +class ThreadContext; + +namespace MipsISA +{ + +inline Tick +handleIprRead(ThreadContext *xc, Packet *pkt) +{ + panic("No implementation for handleIprRead in MIPS\n"); +} + +inline Tick +handleIprWrite(ThreadContext *xc, Packet *pkt) +{ + panic("No implementation for handleIprWrite in MIPS\n"); +} + +} // namespace MipsISA + +#endif diff --git a/src/arch/power/mmaped_ipr.hh b/src/arch/power/mmaped_ipr.hh deleted file mode 100644 index fc88634dc..000000000 --- a/src/arch/power/mmaped_ipr.hh +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * Copyright (c) 2009 The University of Edinburgh - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Stephen Hines - * Timothy M. Jones - */ - -#ifndef __ARCH_POWER_MMAPED_IPR_HH__ -#define __ARCH_POWER_MMAPED_IPR_HH__ - -/** - * @file - * - * ISA-specific helper functions for memory mapped IPR accesses. - */ - -#include "base/misc.hh" -#include "mem/packet.hh" - -class ThreadContext; - -namespace PowerISA -{ - -inline Tick -handleIprRead(ThreadContext *xc, Packet *pkt) -{ - panic("No implementation for handleIprRead in POWER\n"); -} - -inline Tick -handleIprWrite(ThreadContext *xc, Packet *pkt) -{ - panic("No implementation for handleIprWrite in POWER\n"); -} - -} // namespace PowerISA - -#endif // __ARCH_POWER_MMAPED_IPR_HH__ diff --git a/src/arch/power/mmapped_ipr.hh b/src/arch/power/mmapped_ipr.hh new file mode 100644 index 000000000..a55ef8f7d --- /dev/null +++ b/src/arch/power/mmapped_ipr.hh @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * Copyright (c) 2007-2008 The Florida State University + * Copyright (c) 2009 The University of Edinburgh + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Stephen Hines + * Timothy M. Jones + */ + +#ifndef __ARCH_POWER_MMAPPED_IPR_HH__ +#define __ARCH_POWER_MMAPPED_IPR_HH__ + +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "base/misc.hh" +#include "mem/packet.hh" + +class ThreadContext; + +namespace PowerISA +{ + +inline Tick +handleIprRead(ThreadContext *xc, Packet *pkt) +{ + panic("No implementation for handleIprRead in POWER\n"); +} + +inline Tick +handleIprWrite(ThreadContext *xc, Packet *pkt) +{ + panic("No implementation for handleIprWrite in POWER\n"); +} + +} // namespace PowerISA + +#endif // __ARCH_POWER_MMAPPED_IPR_HH__ diff --git a/src/arch/sparc/mmaped_ipr.hh b/src/arch/sparc/mmaped_ipr.hh deleted file mode 100644 index 52310086e..000000000 --- a/src/arch/sparc/mmaped_ipr.hh +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -#ifndef __ARCH_SPARC_MMAPED_IPR_HH__ -#define __ARCH_SPARC_MMAPED_IPR_HH__ - -/** - * @file - * - * ISA-specific helper functions for memory mapped IPR accesses. - */ - -#include "config/full_system.hh" -#include "cpu/thread_context.hh" -#include "mem/packet.hh" -#include "arch/sparc/tlb.hh" - - -namespace SparcISA -{ - -inline Tick -handleIprRead(ThreadContext *xc, Packet *pkt) -{ -#if FULL_SYSTEM - return xc->getDTBPtr()->doMmuRegRead(xc, pkt); -#else - panic("Shouldn't have a memory mapped register in SE\n"); -#endif -} - -inline Tick -handleIprWrite(ThreadContext *xc, Packet *pkt) -{ -#if FULL_SYSTEM - return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); -#else - panic("Shouldn't have a memory mapped register in SE\n"); -#endif -} - - -} // namespace SparcISA - -#endif diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh new file mode 100644 index 000000000..777242e7c --- /dev/null +++ b/src/arch/sparc/mmapped_ipr.hh @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__ +#define __ARCH_SPARC_MMAPPED_IPR_HH__ + +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "config/full_system.hh" +#include "cpu/thread_context.hh" +#include "mem/packet.hh" +#include "arch/sparc/tlb.hh" + + +namespace SparcISA +{ + +inline Tick +handleIprRead(ThreadContext *xc, Packet *pkt) +{ +#if FULL_SYSTEM + return xc->getDTBPtr()->doMmuRegRead(xc, pkt); +#else + panic("Shouldn't have a memory mapped register in SE\n"); +#endif +} + +inline Tick +handleIprWrite(ThreadContext *xc, Packet *pkt) +{ +#if FULL_SYSTEM + return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); +#else + panic("Shouldn't have a memory mapped register in SE\n"); +#endif +} + + +} // namespace SparcISA + +#endif diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 7c7819561..8aa007168 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -816,7 +816,7 @@ handleSparcErrorRegAccess: regAccessOk: handleMmuRegAccess: DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); - req->setFlags(Request::MMAPED_IPR); + req->setFlags(Request::MMAPPED_IPR); req->setPaddr(req->getVaddr()); return NoFault; }; diff --git a/src/arch/x86/mmaped_ipr.hh b/src/arch/x86/mmaped_ipr.hh deleted file mode 100644 index 82fe95cef..000000000 --- a/src/arch/x86/mmaped_ipr.hh +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2007-2008 The Hewlett-Packard Development Company - * All rights reserved. - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_X86_MMAPEDIPR_HH__ -#define __ARCH_X86_MMAPEDIPR_HH__ - -/** - * @file - * - * ISA-specific helper functions for memory mapped IPR accesses. - */ - -#include "arch/x86/regs/misc.hh" -#include "config/full_system.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "mem/packet.hh" - -namespace X86ISA -{ - inline Tick - handleIprRead(ThreadContext *xc, Packet *pkt) - { -#if !FULL_SYSTEM - panic("Shouldn't have a memory mapped register in SE\n"); -#else - Addr offset = pkt->getAddr() & mask(3); - MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg)); - MiscReg data = htog(xc->readMiscReg(index)); - // Make sure we don't trot off the end of data. - assert(offset + pkt->getSize() <= sizeof(MiscReg)); - pkt->setData(((uint8_t *)&data) + offset); -#endif - return xc->getCpuPtr()->ticks(1); - } - - inline Tick - handleIprWrite(ThreadContext *xc, Packet *pkt) - { -#if !FULL_SYSTEM - panic("Shouldn't have a memory mapped register in SE\n"); -#else - Addr offset = pkt->getAddr() & mask(3); - MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg)); - MiscReg data; - data = htog(xc->readMiscRegNoEffect(index)); - // Make sure we don't trot off the end of data. - assert(offset + pkt->getSize() <= sizeof(MiscReg)); - pkt->writeData(((uint8_t *)&data) + offset); - xc->setMiscReg(index, gtoh(data)); -#endif - return xc->getCpuPtr()->ticks(1); - } -}; - -#endif // __ARCH_X86_MMAPEDIPR_HH__ diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh new file mode 100644 index 000000000..525f54bfb --- /dev/null +++ b/src/arch/x86/mmapped_ipr.hh @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2007-2008 The Hewlett-Packard Development Company + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_MMAPPEDIPR_HH__ +#define __ARCH_X86_MMAPPEDIPR_HH__ + +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "arch/x86/regs/misc.hh" +#include "config/full_system.hh" +#include "cpu/base.hh" +#include "cpu/thread_context.hh" +#include "mem/packet.hh" + +namespace X86ISA +{ + inline Tick + handleIprRead(ThreadContext *xc, Packet *pkt) + { +#if !FULL_SYSTEM + panic("Shouldn't have a memory mapped register in SE\n"); +#else + Addr offset = pkt->getAddr() & mask(3); + MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg)); + MiscReg data = htog(xc->readMiscReg(index)); + // Make sure we don't trot off the end of data. + assert(offset + pkt->getSize() <= sizeof(MiscReg)); + pkt->setData(((uint8_t *)&data) + offset); +#endif + return xc->getCpuPtr()->ticks(1); + } + + inline Tick + handleIprWrite(ThreadContext *xc, Packet *pkt) + { +#if !FULL_SYSTEM + panic("Shouldn't have a memory mapped register in SE\n"); +#else + Addr offset = pkt->getAddr() & mask(3); + MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg)); + MiscReg data; + data = htog(xc->readMiscRegNoEffect(index)); + // Make sure we don't trot off the end of data. + assert(offset + pkt->getSize() <= sizeof(MiscReg)); + pkt->writeData(((uint8_t *)&data) + offset); + xc->setMiscReg(index, gtoh(data)); +#endif + return xc->getCpuPtr()->ticks(1); + } +}; + +#endif // __ARCH_X86_MMAPPEDIPR_HH__ diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index dff62a4d7..ac32e86d7 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -179,7 +179,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) panic("CPUID memory space not yet implemented!\n"); } else if (prefix == IntAddrPrefixMSR) { vaddr = vaddr >> 3; - req->setFlags(Request::MMAPED_IPR); + req->setFlags(Request::MMAPPED_IPR); Addr regNum = 0; switch (vaddr & ~IntAddrPrefixMask) { case 0x10: @@ -508,7 +508,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) // space. assert(!(IOPort & ~0xFFFF)); if (IOPort == 0xCF8 && req->getSize() == 4) { - req->setFlags(Request::MMAPED_IPR); + req->setFlags(Request::MMAPPED_IPR); req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); } else if ((IOPort & ~mask(2)) == 0xCFC) { req->setFlags(Request::UNCACHEABLE); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index da4258fb9..27635d3ce 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -29,7 +29,7 @@ */ #include "arch/locked_mem.hh" -#include "arch/mmaped_ipr.hh" +#include "arch/mmapped_ipr.hh" #include "arch/utility.hh" #include "base/bigint.hh" #include "config/the_isa.hh" @@ -334,7 +334,7 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data, Packet::Broadcast); pkt.dataStatic(data); - if (req->isMmapedIpr()) + if (req->isMmappedIpr()) dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); else { if (hasPhysMemPort && pkt.getAddr() == physMemAddr) @@ -501,7 +501,7 @@ AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size, Packet pkt = Packet(req, cmd, Packet::Broadcast); pkt.dataStatic(data); - if (req->isMmapedIpr()) { + if (req->isMmappedIpr()) { dcache_latency += TheISA::handleIprWrite(thread->getTC(), &pkt); } else { diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index ab1ff91e8..632e83356 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -41,7 +41,7 @@ */ #include "arch/locked_mem.hh" -#include "arch/mmaped_ipr.hh" +#include "arch/mmapped_ipr.hh" #include "arch/utility.hh" #include "base/bigint.hh" #include "config/the_isa.hh" @@ -264,7 +264,7 @@ bool TimingSimpleCPU::handleReadPacket(PacketPtr pkt) { RequestPtr req = pkt->req; - if (req->isMmapedIpr()) { + if (req->isMmappedIpr()) { Tick delay; delay = TheISA::handleIprRead(thread->getTC(), pkt); new IprEvent(pkt, this, nextCycle(curTick() + delay)); @@ -401,7 +401,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, { pkt1 = pkt2 = NULL; - assert(!req1->isMmapedIpr() && !req2->isMmapedIpr()); + assert(!req1->isMmappedIpr() && !req2->isMmappedIpr()); if (req->getFlags().isSet(Request::NO_ACCESS)) { buildPacket(pkt1, req, read); @@ -536,7 +536,7 @@ bool TimingSimpleCPU::handleWritePacket() { RequestPtr req = dcache_pkt->req; - if (req->isMmapedIpr()) { + if (req->isMmappedIpr()) { Tick delay; delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay)); diff --git a/src/mem/physical.cc b/src/mem/physical.cc index a134165bc..e7c96ab54 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -548,7 +548,7 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string §ion) fatal("Insufficient memory to allocate compression state for %s\n", filename); - // unmap file that was mmaped in the constructor + // unmap file that was mmapped in the constructor // This is done here to make sure that gzip and open don't muck with our // nice large space of memory before we reallocate it munmap((char*)pmemAddr, size()); diff --git a/src/mem/request.hh b/src/mem/request.hh index ec1b8ba29..4aa3a821a 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -70,7 +70,7 @@ class Request : public FastAlloc /** The request is to an uncacheable address. */ static const FlagsType UNCACHEABLE = 0x00001000; /** This request is to a memory mapped register. */ - static const FlagsType MMAPED_IPR = 0x00002000; + static const FlagsType MMAPPED_IPR = 0x00002000; /** This request is a clear exclusive. */ static const FlagsType CLEAR_LL = 0x00004000; @@ -453,7 +453,7 @@ class Request : public FastAlloc bool isLocked() const { return _flags.isSet(LOCKED); } bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); } bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); } - bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); } + bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); } bool isClearLL() const { return _flags.isSet(CLEAR_LL); } };