From: Andrey Miroshnikov Date: Mon, 20 Jun 2022 12:53:18 +0000 (+0100) Subject: Added extra notes after watching Luke's comparison vid X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=57a3aaad2ae0f427bdbb137cc2a4d6c1f6775f5d;p=libreriscv.git Added extra notes after watching Luke's comparison vid --- diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex index 99e800f98..91da580f3 100644 --- a/svp64-primer/summary.tex +++ b/svp64-primer/summary.tex @@ -106,8 +106,8 @@ overlaying the Vector Registers onto the Floating Point registers, similar to x86 "MMX". Simple-V's "Vector" Registers are specifically designed to fit -on top of the Scalar (GPR, FPR) register files, which are extended from -32 to 128 entries. This is a primary reason why Simple-V can be added +on top of the Scalar (GPR, FPR) register files with \textbf{(byte-addressable access required?)}, which are extended from + the default of 32 (see PowerISA 3.2.1 General Purpose Registers and 4.2.1 Floating-Point Registers \textbf{[WHICH SPEC VERSION?]}), to 128 entries in the Libre-SOC implementation \textbf{[CAN WE REFER TO LIBRE-SOC?]}. This is a primary reason why Simple-V can be added on top of an existing Scalar ISA, and \textit{in particular} why there is no need to add Vector Registers or Vector instructions.