From: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date: Sun, 29 Aug 2021 18:22:22 +0000 (+0000)
Subject: fixedarith: switch divweX to XLEN
X-Git-Tag: xlen-bcd~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=57a6c00ca9094b316087c07edfd7f12034575f7c;p=openpower-isa.git

fixedarith: switch divweX to XLEN
---

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index 365809f3..d6aca118 100644
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -442,23 +442,23 @@ XO-Form
 
 Pseudo-code:
 
-    dividend[0:63] <- (RA)[32:63] || [0]*32
-    divisor[0:63] <- EXTS64((RB)[32:63])
-    if (((dividend = 0x8000_0000_0000_0000) &
-         (divisor = [1]*64)) |
-         (divisor = [0]*64)) then
+    dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
+    divisor[0:XLEN-1] <- EXTS64((RB)[XLEN/2:XLEN-1])
+    if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
+         (divisor = [1]*XLEN)) |
+         (divisor = [0]*XLEN)) then
         overflow <- 1
     else
         result <- DIVS(dividend, divisor)
-        result32[0:63] <- EXTS64(result[32:63])
-        if (result32 = result) then
-            RT[32:63] <- result[32:63]
-            RT[0:31] <- undefined([0]*32)
+        result_half[0:XLEN-1] <- EXTS64(result[XLEN/2:XLEN-1])
+        if (result_half = result) then
+            RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
+            RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
             overflow <- 0
         else
             overflow <- 1
     if overflow = 1 then
-        RT[0:63] <- undefined([0]*64)
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
 
 Special Registers Altered: