From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Oct 2018 02:21:33 +0000 (+0000)
Subject: return correct register elwidth for get_fpreg
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=57ad0483f9e46fce75ef847e026bf5078fa91b12;p=riscv-isa-sim.git

return correct register elwidth for get_fpreg
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 9d903d5..a7ef40f 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -208,8 +208,10 @@ sv_reg_t sv_proc_t::get_intreg(reg_spec_t const&spec)
 sv_freg_t sv_proc_t::get_fpreg(reg_spec_t const&spec)
 {
     freg_t data = READ_FREG(spec);
-    uint8_t bitwidth = _insn->src_bitwidth;
-    return sv_freg_t(data, xlen, bitwidth);
+    //uint8_t bitwidth = _insn->src_bitwidth;
+    reg_t reg = spec.reg;
+    uint8_t elwidth = _insn->reg_elwidth(reg, false);
+    return sv_freg_t(data, xlen, elwidth);
 }
 
 #define GET_REG(name) \
@@ -453,7 +455,12 @@ sv_float32_t (sv_proc_t::f32)(sv_freg_t x)
         case 1: throw trap_illegal_instruction(0); // XXX for now
         // 16-bit data, up-convert to f32
         case 2:
-            return f16_to_f32(f16(x.to_uint32()));
+        {
+            sv_reg_t x32(x.to_uint32());
+            float16_t f_16 = f16(x);
+            fprintf(stderr, "f16-to-f32 %lx\n", (uint64_t)x32);
+            return f16_to_f32(f_16);
+        }
         // 0 and 3 are 32-bit
         default: break;
     }
@@ -469,6 +476,7 @@ sv_float32_t (sv_proc_t::f32)(sv_reg_t const& v)
         case 1: throw trap_illegal_instruction(0); // XXX for now
         // 16-bit data, up-convert to f32
         case 2:
+            fprintf(stderr, "f16-to-f32\n");
             return f16_to_f32(f16(x));
         // 0 and 3 are 32-bit
         default: break;