From: N. Engelhardt <nak@yosyshq.com>
Date: Fri, 15 Apr 2022 13:10:48 +0000 (+0200)
Subject: verific: allow memories to be inferred in loops
X-Git-Tag: yosys-0.17~27^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=57bc29c64a546fc1dc9a14f0d19a1e30fb5948f0;p=yosys.git

verific: allow memories to be inferred in loops
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 44196a310..b53bad7da 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2548,6 +2548,7 @@ struct VerificPass : public Pass {
 
 			RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
+			RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
 
 #ifdef VERIFIC_VHDL_SUPPORT
 			RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);