From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 19 Jun 2019 15:02:18 +0000 (+0100)
Subject: add SV VLIW idea
X-Git-Tag: convert-csv-opcode-to-binary~4596
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=57c95a3889819a7b3e3565c17744582532af9114;p=libreriscv.git

add SV VLIW idea
---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 3d0838a78..bbed33931 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2233,6 +2233,7 @@ Reminder of the variable-length format from Section 1.5 of the RISC-V ISA:
 | base+4 | base+2           | base             | number of bits             |
 | ------ | ---------------- | ---------------- | -------------------------- |
 | ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
+| {ops}{Pred}{Reg}{VL}     || SV Prefix        |                            |
 
 Notes: