From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 24 Oct 2020 18:41:21 +0000 (+0000)
Subject: add feedback shift register back in
X-Git-Tag: partial-core-ls180-gdsii~36
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=57d8ffdf130b300d58b6461a2e57f560caf97238;p=soclayout.git

add feedback shift register back in
---

diff --git a/experiments10/add.py b/experiments10/add.py
index 19a9004..551b277 100644
--- a/experiments10/add.py
+++ b/experiments10/add.py
@@ -32,7 +32,7 @@ class ADD(Elaboratable):
         m = Module()
 
         m.submodules.jtag = jtag = self.jtag
-        #m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
+        m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
 
         # do a simple "add"
         m.d.sync += self.f.eq(self.a + self.b)
diff --git a/experiments10/non_generated/add.il b/experiments10/non_generated/add.il
index 37b08ae..2de11d3 100644
--- a/experiments10/non_generated/add.il
+++ b/experiments10/non_generated/add.il
@@ -961,18 +961,22 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "add.jtag"
 module \jtag
+  attribute \src "add.py:29"
+  wire width 3 input 0 \sr0__i
+  attribute \src "add.py:29"
+  wire width 3 output 1 \sr0__o
   attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
+  wire width 1 input 2 \rst
   attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  wire width 1 input 3 \clk
   attribute \src "add.py:22"
-  wire width 1 input 2 \tdi
+  wire width 1 input 4 \tdi
   attribute \src "add.py:22"
-  wire width 1 output 3 \tdo
+  wire width 1 output 5 \tdo
   attribute \src "add.py:22"
-  wire width 1 input 4 \tck
+  wire width 1 input 6 \tck
   attribute \src "add.py:22"
-  wire width 1 input 5 \tms
+  wire width 1 input 7 \tms
   attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
   wire width 1 \posjtag_clk
   attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
@@ -1388,8 +1392,6 @@ module \jtag
     end
     sync init
   end
-  attribute \src "add.py:29"
-  wire width 3 \sr0__o
   attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:638"
   wire width 3 \sr0_reg
   attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:638"
@@ -1600,8 +1602,6 @@ module \jtag
     sync posedge \clk
       update \sr0__oe \sr0__oe$next
   end
-  attribute \src "add.py:29"
-  wire width 3 \sr0__i
   process $group_14
     assign \sr0_reg$next \sr0_reg
     attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:669"
@@ -1639,7 +1639,6 @@ module \jtag
     end
     sync init
   end
-  connect \sr0__i 3'000
 end
 attribute \generator "nMigen"
 attribute \top 1
@@ -1665,7 +1664,13 @@ module \add
   wire width 1 input 7 \clk
   attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 8 \rst
+  attribute \src "add.py:29"
+  wire width 3 \jtag_sr0__i
+  attribute \src "add.py:29"
+  wire width 3 \jtag_sr0__o
   cell \jtag \jtag
+    connect \sr0__i \jtag_sr0__i
+    connect \sr0__o \jtag_sr0__o
     connect \rst \rst
     connect \clk \clk
     connect \tdi \tdi
@@ -1673,6 +1678,11 @@ module \add
     connect \tck \tck
     connect \tms \tms
   end
+  process $group_0
+    assign \jtag_sr0__i 3'000
+    assign \jtag_sr0__i \jtag_sr0__o
+    sync init
+  end
   attribute \src "add.py:38"
   wire width 5 $1
   attribute \src "add.py:38"
@@ -1689,7 +1699,7 @@ module \add
     connect \Y $2
   end
   connect $1 $2
-  process $group_0
+  process $group_1
     assign \f$next \f
     assign \f$next $1 [3:0]
     attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"