From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Oct 2018 22:43:38 +0000 (+0100)
Subject: fix debug printfs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=57e5e224c00ffd2160e72c959179088ff037d7b9;p=riscv-isa-sim.git

fix debug printfs
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 118c972..1bc3721 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -12,7 +12,8 @@
 #include "sv_insn_redirect.h"
 
 #ifdef INSN_TYPE_BRANCH
-    #define set_pc(x) insn.setpc(xlen, vlen, npc, x, *dest_offs, target_reg);
+    #define set_pc(x) insn.setpc(xlen, vlen, npc, x, \
+                                 *dest_offs, target_reg);
 #else
     #define set_pc _set_pc
 #endif
@@ -139,7 +140,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   {
     insn.reset_vloop_check();
 #ifdef INSN_C_BEQZ
-        fprintf(stderr, "pre twin reg %s src %d dest %d pred %lx %lx\n",
+        fprintf(stderr, "pre twin reg %s src %lx dest %d pred %lx %lx\n",
             xstr(INSN), _target_reg, *dest_offs, target_pred, dest_pred);
 #endif
 #ifdef INSN_CATEGORY_TWINPREDICATION
@@ -182,7 +183,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
 #ifdef INSN_C_SWSP
     fprintf(stderr, "pre %s %x vloop %d %d %d" \
-                      "vlen %d stop %d pred %lx rdv %lx v %d rvc2 %ld sp %lx\n",
+                      "vlen %d stop %d pred %lx rdv %lx v %ld rvc2 %ld sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rvc_rs2()),
@@ -197,8 +198,8 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
                 insn._rd(), insn.rvc_lwsp_imm(), READ_REG(sp));
 #endif
 #ifdef INSN_C_BEQZ
-    fprintf(stderr, "pre %s %x vloop %d %d %d" \
-                      "vlen %d stop %d pred %lx rdv %lx rvc_rs1 %d\n",
+    fprintf(stderr, "pre %s %x vloop %d %ld %d" \
+                      "vlen %d stop %d pred %lx rdv %lx rvc_rs1 %ld\n",
                 xstr(INSN), INSNCODE, voffs, _target_reg, *dest_offs,
                 vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rvc_rs1s()),