From: Sandra Loosemore Date: Tue, 24 Oct 2017 02:39:11 +0000 (-0400) Subject: cdx-branch.c: Fix broken test. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=57f6a200e324c605ed19fef107e528d0b902770a;p=gcc.git cdx-branch.c: Fix broken test. 2017-10-23 Sandra Loosemore gcc/testsuite/ * gcc.target/nios2/cdx-branch.c: Fix broken test. * gcc.target/nios2/lo-addr-bypass.c: New. * gcc.target/nios2/lo-addr-char.c: New. * gcc.target/nios2/lo-addr-int.c: New. * gcc.target/nios2/lo-addr-pic.c: New. * gcc.target/nios2/lo-addr-short.c: New. * gcc.target/nios2/lo-addr-tls.c: New. * gcc.target/nios2/lo-addr-uchar.c: New. * gcc.target/nios2/lo-addr-ushort.c: New. * gcc.target/nios2/lo-addr-volatile.c: New. From-SVN: r254035 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d63fd0b5389..f188d8181e5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2017-10-23 Sandra Loosemore + + * gcc.target/nios2/cdx-branch.c: Fix broken test. + * gcc.target/nios2/lo-addr-bypass.c: New. + * gcc.target/nios2/lo-addr-char.c: New. + * gcc.target/nios2/lo-addr-int.c: New. + * gcc.target/nios2/lo-addr-pic.c: New. + * gcc.target/nios2/lo-addr-short.c: New. + * gcc.target/nios2/lo-addr-tls.c: New. + * gcc.target/nios2/lo-addr-uchar.c: New. + * gcc.target/nios2/lo-addr-ushort.c: New. + * gcc.target/nios2/lo-addr-volatile.c: New. + 2017-10-23 Paolo Carlini PR c++/80449 diff --git a/gcc/testsuite/gcc.target/nios2/cdx-branch.c b/gcc/testsuite/gcc.target/nios2/cdx-branch.c index 3b984f2712a..3a9c459cec3 100644 --- a/gcc/testsuite/gcc.target/nios2/cdx-branch.c +++ b/gcc/testsuite/gcc.target/nios2/cdx-branch.c @@ -23,7 +23,7 @@ extern int i (int); extern int j (int); extern int k (int); -int h (int a) +int h (int a, int b) { int x; @@ -31,7 +31,7 @@ int h (int a) an unconditional branch from one branch of the "if" to the return statement. We compile this testcase with -Os to avoid insertion of a duplicate epilogue in place of the branch. */ - if (a == 1) + if (a == b) x = i (37); else x = j (42); diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-bypass.c b/gcc/testsuite/gcc.target/nios2/lo-addr-bypass.c new file mode 100644 index 00000000000..24e6cfd4cc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-bypass.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=r2 -mbypass-cache" } */ +/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 12 } } */ +/* { dg-final { scan-assembler-not "ldw\t" } } */ +/* { dg-final { scan-assembler-not "stw\t" } } */ +/* { dg-final { scan-assembler-not "ldwio\tr., %lo" } } */ +/* { dg-final { scan-assembler-not "stwio\tr., %lo" } } */ + +/* Check that we do not generate %lo addresses with R2 ldstio instructions. + %lo requires a 16-bit relocation and on R2 these instructions only have a + 12-bit register offset. */ +#define TYPE int + +struct ss +{ + TYPE x1,x2; +}; + +extern TYPE S1; +extern TYPE S2[]; + +extern struct ss S3; +extern struct ss S4[]; + +TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } + diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-char.c b/gcc/testsuite/gcc.target/nios2/lo-addr-char.c new file mode 100644 index 00000000000..dd992458323 --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-char.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */ +/* { dg-final { scan-assembler-times "ldbu\tr., %lo" 4 } } */ +/* { dg-final { scan-assembler-times "ldb\tr., %lo" 16 } } */ +/* { dg-final { scan-assembler-times "stb\tr., %lo" 4 } } */ + +/* Check that various address forms involving a symbolic constant + with a possible constant offset and/or index register are optimized + to generate a %lo relocation in the load/store instructions instead + of a plain register indirect addressing mode. */ +/* Note: get* uses ldhu but ext* uses ldh since TYPE is signed. */ + +#define TYPE signed char + +struct ss +{ + TYPE x1,x2; +}; + +extern TYPE S1; +extern TYPE S2[]; + +extern struct ss S3; +extern struct ss S4[]; + +TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } + +int extw1 (void) { return (int)(S1); } +int extw2 (int i) { return (int)(S2[i]); } +int extw3 (void) { return (int)(S3.x2); } +int extw4 (int i) { return (int)(S4[i].x2); } +unsigned int extwu1 (void) { return (unsigned int)(S1); } +unsigned int extwu2 (int i) { return (unsigned int)(S2[i]); } +unsigned int extwu3 (void) { return (unsigned int)(S3.x2); } +unsigned int extwu4 (int i) { return (unsigned int)(S4[i].x2); } + +short exth1 (void) { return (short)(S1); } +short exth2 (int i) { return (short)(S2[i]); } +short exth3 (void) { return (short)(S3.x2); } +short exth4 (int i) { return (short)(S4[i].x2); } +unsigned short exthu1 (void) { return (unsigned short)(S1); } +unsigned short exthu2 (int i) { return (unsigned short)(S2[i]); } +unsigned short exthu3 (void) { return (unsigned short)(S3.x2); } +unsigned short exthu4 (int i) { return (unsigned short)(S4[i].x2); } + diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-int.c b/gcc/testsuite/gcc.target/nios2/lo-addr-int.c new file mode 100644 index 00000000000..9a6f779d383 --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-int.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */ +/* { dg-final { scan-assembler-times "ldw\tr., %lo" 4 } } */ +/* { dg-final { scan-assembler-times "stw\tr., %lo" 4 } } */ + +/* Check that various address forms involving a symbolic constant + with a possible constant offset and/or index register are optimized + to generate a %lo relocation in the load/store instructions instead + of a plain register indirect addressing mode. */ + +#define TYPE int + +struct ss +{ + TYPE x1,x2; +}; + +extern TYPE S1; +extern TYPE S2[]; + +extern struct ss S3; +extern struct ss S4[]; + +TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } + diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-pic.c b/gcc/testsuite/gcc.target/nios2/lo-addr-pic.c new file mode 100644 index 00000000000..bcd623785bd --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-pic.c @@ -0,0 +1,38 @@ +/* { dg-do compile { target nios2-*-linux-gnu } } */ +/* { dg-options "-O2 -fpic" } */ +/* { dg-final { scan-assembler-not "ldw\tr., %lo" } } */ +/* { dg-final { scan-assembler-not "stw\tr., %lo" } } */ + +/* Check that address transformations for symbolic constants do NOT + apply to code compiled with -fPIC, which requires references to + go through the GOT pointer (r22) instead. */ + +#define TYPE int + +struct ss +{ + TYPE x1,x2; +}; + +extern TYPE S1; +extern TYPE S2[]; + +extern struct ss S3; +extern struct ss S4[]; + +TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } + diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-short.c b/gcc/testsuite/gcc.target/nios2/lo-addr-short.c new file mode 100644 index 00000000000..792ec227291 --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-short.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */ +/* { dg-final { scan-assembler-times "ldhu\tr., %lo" 4 } } */ +/* { dg-final { scan-assembler-times "ldh\tr., %lo" 8 } } */ +/* { dg-final { scan-assembler-times "sth\tr., %lo" 4 } } */ + +/* Check that various address forms involving a symbolic constant + with a possible constant offset and/or index register are optimized + to generate a %lo relocation in the load/store instructions instead + of a plain register indirect addressing mode. */ +/* Note: get* uses ldhu but ext* uses ldh since TYPE is signed. */ + +#define TYPE short + +struct ss +{ + TYPE x1,x2; +}; + +extern TYPE S1; +extern TYPE S2[]; + +extern struct ss S3; +extern struct ss S4[]; + +TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } + +int extw1 (void) { return (int)(S1); } +int extw2 (int i) { return (int)(S2[i]); } +int extw3 (void) { return (int)(S3.x2); } +int extw4 (int i) { return (int)(S4[i].x2); } +unsigned int extwu1 (void) { return (unsigned int)(S1); } +unsigned int extwu2 (int i) { return (unsigned int)(S2[i]); } +unsigned int extwu3 (void) { return (unsigned int)(S3.x2); } +unsigned int extwu4 (int i) { return (unsigned int)(S4[i].x2); } + diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-tls.c b/gcc/testsuite/gcc.target/nios2/lo-addr-tls.c new file mode 100644 index 00000000000..d56fbc2ed81 --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-tls.c @@ -0,0 +1,38 @@ +/* { dg-require-effective-target tls } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "ldw\tr., %lo" } } */ +/* { dg-final { scan-assembler-not "stw\tr., %lo" } } */ + +/* Check that address transformations for symbolic constants do NOT + apply to TLS variables. */ + +#define TYPE int + +struct ss +{ + TYPE x1,x2; +}; + +extern __thread TYPE S1; +extern __thread TYPE S2[]; + +extern __thread struct ss S3; +extern __thread struct ss S4[]; + +TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } + diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-uchar.c b/gcc/testsuite/gcc.target/nios2/lo-addr-uchar.c new file mode 100644 index 00000000000..e9733afde4a --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-uchar.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */ +/* { dg-final { scan-assembler-times "ldbu\tr., %lo" 20 } } */ +/* { dg-final { scan-assembler-times "stb\tr., %lo" 4 } } */ + +/* Check that various address forms involving a symbolic constant + with a possible constant offset and/or index register are optimized + to generate a %lo relocation in the load/store instructions instead + of a plain register indirect addressing mode. */ + +#define TYPE unsigned char + +struct ss +{ + TYPE x1,x2; +}; + +extern TYPE S1; +extern TYPE S2[]; + +extern struct ss S3; +extern struct ss S4[]; + +TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } + +int extw1 (void) { return (int)(S1); } +int extw2 (int i) { return (int)(S2[i]); } +int extw3 (void) { return (int)(S3.x2); } +int extw4 (int i) { return (int)(S4[i].x2); } +unsigned int extwu1 (void) { return (unsigned int)(S1); } +unsigned int extwu2 (int i) { return (unsigned int)(S2[i]); } +unsigned int extwu3 (void) { return (unsigned int)(S3.x2); } +unsigned int extwu4 (int i) { return (unsigned int)(S4[i].x2); } + +short exth1 (void) { return (short)(S1); } +short exth2 (int i) { return (short)(S2[i]); } +short exth3 (void) { return (short)(S3.x2); } +short exth4 (int i) { return (short)(S4[i].x2); } +unsigned short exthu1 (void) { return (unsigned short)(S1); } +unsigned short exthu2 (int i) { return (unsigned short)(S2[i]); } +unsigned short exthu3 (void) { return (unsigned short)(S3.x2); } +unsigned short exthu4 (int i) { return (unsigned short)(S4[i].x2); } + diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-ushort.c b/gcc/testsuite/gcc.target/nios2/lo-addr-ushort.c new file mode 100644 index 00000000000..4a19c13bf2c --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-ushort.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */ +/* { dg-final { scan-assembler-times "ldhu\tr., %lo" 12 } } */ +/* { dg-final { scan-assembler-times "sth\tr., %lo" 4 } } */ + +/* Check that various address forms involving a symbolic constant + with a possible constant offset and/or index register are optimized + to generate a %lo relocation in the load/store instructions instead + of a plain register indirect addressing mode. */ + +#define TYPE unsigned short + +struct ss +{ + TYPE x1,x2; +}; + +extern TYPE S1; +extern TYPE S2[]; + +extern struct ss S3; +extern struct ss S4[]; + +TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } + +int extw1 (void) { return (int)(S1); } +int extw2 (int i) { return (int)(S2[i]); } +int extw3 (void) { return (int)(S3.x2); } +int extw4 (int i) { return (int)(S4[i].x2); } +unsigned int extwu1 (void) { return (unsigned int)(S1); } +unsigned int extwu2 (int i) { return (unsigned int)(S2[i]); } +unsigned int extwu3 (void) { return (unsigned int)(S3.x2); } +unsigned int extwu4 (int i) { return (unsigned int)(S4[i].x2); } + diff --git a/gcc/testsuite/gcc.target/nios2/lo-addr-volatile.c b/gcc/testsuite/gcc.target/nios2/lo-addr-volatile.c new file mode 100644 index 00000000000..40a8be429bf --- /dev/null +++ b/gcc/testsuite/gcc.target/nios2/lo-addr-volatile.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=r2 -mno-cache-volatile" } */ +/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 12 } } */ +/* { dg-final { scan-assembler-not "ldw\t" } } */ +/* { dg-final { scan-assembler-not "stw\t" } } */ +/* { dg-final { scan-assembler-not "ldwio\tr., %lo" } } */ +/* { dg-final { scan-assembler-not "stwio\tr., %lo" } } */ + +/* Check that we do not generate %lo addresses with R2 ldstio instructions. + %lo requires a 16-bit relocation and on R2 these instructions only have a + 12-bit register offset. */ + +#define TYPE int + +struct ss +{ + TYPE x1,x2; +}; + +extern volatile TYPE S1; +extern volatile TYPE S2[]; + +extern volatile struct ss S3; +extern volatile struct ss S4[]; + +volatile TYPE *addr1 (void) { return &S1; } +TYPE get1 (void) { return S1; } +void set1 (TYPE value) { S1 = value; } + +volatile TYPE *addr2 (int i) { return &(S2[i]); } +TYPE get2 (int i) { return S2[i]; } +void set2 (int i, TYPE value) { S2[i] = value; } + +volatile TYPE *addr3 (void) { return &(S3.x2); } +TYPE get3 (void) { return S3.x2; } +void set3 (TYPE value) { S3.x2 = value; } + +volatile TYPE *addr4 (int i) { return &(S4[i].x2); } +TYPE get4 (int i) { return S4[i].x2; } +void set4 (int i, TYPE value) { S4[i].x2 = value; } +