From: Marek Olšák <marek.olsak@amd.com>
Date: Sun, 6 Sep 2015 15:35:06 +0000 (+0200)
Subject: gallium/radeon: add separate stencil level dirty flags
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5804c6adf8361adb5d04feaf578dffbf840475d6;p=mesa.git

gallium/radeon: add separate stencil level dirty flags

We will only do depth-only or stencil-only decompress blits, whichever is
needed by textures, instead of always doing both.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
---

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index a5caa0dac2b..6169c5b719b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3375,11 +3375,11 @@ static void evergreen_dma_copy(struct pipe_context *ctx,
 	}
 
 	if (src->format != dst->format || src_box->depth > 1 ||
-	    rdst->dirty_level_mask != 0) {
+	    (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
 		goto fallback;
 	}
 
-	if (rsrc->dirty_level_mask) {
+	if (rsrc->dirty_level_mask & (1 << src_level)) {
 		ctx->flush_resource(ctx, src);
 	}
 
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index a16f1c25dcb..178005a8574 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1779,6 +1779,9 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		struct r600_texture *rtex = (struct r600_texture *)surf->texture;
 
 		rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+
+		if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+			rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
 	}
 	if (rctx->framebuffer.compressed_cb_mask) {
 		struct pipe_surface *surf;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 0f9b91af315..b58b500bd76 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -205,6 +205,7 @@ struct r600_texture {
 	unsigned			pitch_override;
 	bool				is_depth;
 	unsigned			dirty_level_mask; /* each bit says if that mipmap is compressed */
+	unsigned			stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 	struct r600_texture		*flushed_depth_texture;
 	boolean				is_flushing_texture;
 	struct radeon_surf		surface;
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c
index 691d379bccd..6454b8ce8c0 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -242,7 +242,7 @@ void cik_sdma_copy(struct pipe_context *ctx,
 
 	if (src->format != dst->format ||
 	    rdst->surface.nsamples > 1 || rsrc->surface.nsamples > 1 ||
-	    rdst->dirty_level_mask & (1 << dst_level)) {
+	    (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
 		goto fallback;
 	}
 
diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index 3d980fb67b8..31b0b41e5a4 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -246,13 +246,13 @@ void si_dma_copy(struct pipe_context *ctx,
 	goto fallback;
 
 	if (src->format != dst->format || src_box->depth > 1 ||
-	    rdst->dirty_level_mask != 0 ||
+	    (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level) ||
 	    rdst->cmask.size || rdst->fmask.size ||
 	    rsrc->cmask.size || rsrc->fmask.size) {
 		goto fallback;
 	}
 
-	if (rsrc->dirty_level_mask) {
+	if (rsrc->dirty_level_mask & (1 << src_level)) {
 		ctx->flush_resource(ctx, src);
 	}
 
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index fb65eb3ce2d..43170ec446b 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -858,6 +858,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		struct r600_texture *rtex = (struct r600_texture *)surf->texture;
 
 		rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+
+		if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+			rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
 	}
 	if (sctx->framebuffer.compressed_cb_mask) {
 		struct pipe_surface *surf;