From: Hoa Nguyen <hoanguyen@ucdavis.edu>
Date: Fri, 20 Nov 2020 04:08:14 +0000 (-0800)
Subject: mem-ruby: Fix cache hits being profiled as cache misses
X-Git-Tag: develop-gem5-snapshot~426
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=580eb6419590811554b5521a6a1df336e5d0b3e7;p=gem5.git

mem-ruby: Fix cache hits being profiled as cache misses

There are some instances where a cache hit is profiled as a cache
miss. This commit addresses this error.

Change-Id: I7dafa806ef3f1e3717650dc25f8657a0ea741dd1
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37835
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/mem/ruby/protocol/MI_example-cache.sm b/src/mem/ruby/protocol/MI_example-cache.sm
index 8738f336e..2c9bdb789 100644
--- a/src/mem/ruby/protocol/MI_example-cache.sm
+++ b/src/mem/ruby/protocol/MI_example-cache.sm
@@ -353,7 +353,7 @@ machine(MachineType:L1Cache, "MI Example L1 Cache")
       ++cacheMemory.demand_misses;
   }
 
-  action(p_profileHit, "ph", desc="Profile cache miss") {
+  action(p_profileHit, "ph", desc="Profile cache hit") {
       ++cacheMemory.demand_hits;
   }
 
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
index a9589d63a..fb957f087 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
@@ -1283,19 +1283,19 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
   }
 
   action(l10h_profileHit, "l10h", desc="l10h hit profile") {
-    ++L1D0cache.demand_misses;
+    ++L1D0cache.demand_hits;
   }
 
   action(l11h_profileHit, "l11h", desc="l11h hit profile") {
-    ++L1D1cache.demand_misses;
+    ++L1D1cache.demand_hits;
   }
 
   action(l1ih_profileHit, "l1lh", desc="l1ih hit profile") {
-    ++L1Icache.demand_misses;
+    ++L1Icache.demand_hits;
   }
 
   action(l2h_profileHit, "l2h", desc="l2h hit profile") {
-    ++L2cache.demand_misses;
+    ++L2cache.demand_hits;
   }
 
   action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {
diff --git a/src/mem/ruby/protocol/MOESI_hammer-cache.sm b/src/mem/ruby/protocol/MOESI_hammer-cache.sm
index 8541f3541..5440eb8e2 100644
--- a/src/mem/ruby/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-cache.sm
@@ -1285,12 +1285,12 @@ machine(MachineType:L1Cache, "AMD Hammer-like protocol")
       ++L2cache.demand_misses;
   }
 
-  action(uu_profileL2Hit, "\uh", desc="Profile the demand hits ") {
+  action(uu_profileL2Hit, "\uh", desc="Profile the demand hits") {
       ++L2cache.demand_hits;
   }
 
   action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
-    stall_and_wait(mandatoryQueue_in, address);    
+    stall_and_wait(mandatoryQueue_in, address);
   }
 
   action(z_stall, "z", desc="stall") {