From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 07:07:17 +0000 (-0700)
Subject: Add unsigned case
X-Git-Tag: working-ls180~1058^2~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=580faae8ad608981ef6ef6a99ca6b771dc0368ae;p=yosys.git

Add unsigned case
---

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 33555264d..e930015a4 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -47,6 +47,23 @@ select -assert-count 0 t:*
 
 ####################
 
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
+    always @(posedge clk) if (ce) o <= i;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt -assert peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+####################
+
 design -reset
 read_verilog <<EOT
 module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);