From: lkcl <lkcl@web>
Date: Tue, 4 Aug 2020 09:09:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2294
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=581f90e151e3cfa26c72f1eca1a697237d8a6c7c;p=libreriscv.git

---

diff --git a/lkcl.mdwn b/lkcl.mdwn
index 9dbc3a122..4c37ade64 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -24,7 +24,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
@@ -41,6 +40,7 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted:
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe