From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Oct 2018 03:12:39 +0000 (+0100)
Subject: sign/zero-extend result as well
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=581fc4f437fbb879896f16bc37bf71c1f737f069;p=riscv-isa-sim.git

sign/zero-extend result as well
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index d98f0d8..3c9fa05 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -347,6 +347,7 @@ sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs)
     }
     uint64_t vlhs = 0;
     uint64_t vrhs = 0;
+    uint64_t result = 0;
     // sign-extend or zero-extend to max bitwidth of lhs and rhs?
     // has the effect of truncating, as well.
     if (_insn->signextended) { // sign-extend?
@@ -356,7 +357,13 @@ sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs)
         vlhs = zext_bwid(lhs, bitwidth);
         vrhs = zext_bwid(rhs, bitwidth);
     }
-    return sv_reg_t(vlhs + vrhs, xlen); // XXX TODO: bitwidth
+    result = vlhs + vrhs;
+    if (_insn->signextended) { // sign-extend?
+        result = sext_bwid(result, bitwidth);
+    } else { // nope: zero-extend.
+        result = zext_bwid(result, bitwidth);
+    }
+    return sv_reg_t(result, xlen); // XXX TODO: bitwidth
 }
 
 sv_reg_t sv_proc_t::rv_sub(sv_reg_t const & lhs, sv_reg_t const & rhs)