From: Luke Kenneth Casson Leighton Date: Sun, 31 May 2020 11:54:53 +0000 (+0100) Subject: add in more CR debug statements X-Git-Tag: div_pipeline~721 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=584c19adf217c55eec3de5618e4cba47494a4536;p=soc.git add in more CR debug statements --- diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 34ae0eae..ec738383 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -241,12 +241,14 @@ class TestRunner(FHDLTestCase): cridx_ok = yield dec2.e.write_cr.ok cridx = yield dec2.e.write_cr.data + print ("check extra output", repr(code), cridx_ok, cridx) if rc: self.assertEqual(cridx, 0, code) if cridx_ok: cr_expected = sim.crl[cridx].get_range().value cr_actual = yield alu.n.data_o.cr0.data + print ("CR", cridx, cr_expected, cr_actual) self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code)) cry_out = yield dec2.e.output_carry diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index 049a276e..b5d55a4b 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -229,6 +229,8 @@ class TestRunner(FHDLTestCase): cridx_ok = yield dec2.e.write_cr.ok cridx = yield dec2.e.write_cr.data + print ("check extra output", repr(code), cridx_ok, cridx) + if rc: self.assertEqual(cridx_ok, 1, code) self.assertEqual(cridx, 0, code) @@ -236,6 +238,7 @@ class TestRunner(FHDLTestCase): if cridx_ok: cr_expected = sim.crl[cridx].get_range().value cr_actual = yield from get_cu_output(cu, 1, code) + print ("CR", cridx, cr_expected, cr_actual) self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code)) cry_out = yield dec2.e.output_carry