From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 29 Mar 2019 15:32:44 +0000 (+0100)
Subject: Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
X-Git-Tag: yosys-0.9~211^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=584d2030bf53c703febe8fda9cae73c72416c6cc;p=yosys.git

Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index dbaace585..0a1f97ac0 100644
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -14,6 +14,8 @@ frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
 	$(Q) mkdir -p $(dir $@)
 	$(P) flex -o frontends/verilog/verilog_lexer.cc $<
 
+frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=100000
+
 OBJS += frontends/verilog/verilog_parser.tab.o
 OBJS += frontends/verilog/verilog_lexer.o
 OBJS += frontends/verilog/preproc.o