From: Simon Dardis Date: Wed, 12 Aug 2015 10:44:56 +0000 (+0100) Subject: [MIPS] Scheduler fix for the 74k & 24k. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=585d372b05f822f9c77cad2284c034d87a297564;p=gcc.git [MIPS] Scheduler fix for the 74k & 24k. 2015-08-12 Simon Dardis gcc/ * config/mips/mips.c (mips_store_data_bypass_p): Bring code into line with comments. * config/mips/sb1.md: Update usage of mips_store_data_bypass_p. From-SVN: r226805 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 62b38279ab0..2e94a8d43df 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-08-12 Simon Dardis + + * config/mips/mips.c (mips_store_data_bypass_p): Bring code into + line with comments. + * config/mips/sb1.md: Update usage of mips_store_data_bypass_p. + 2015-08-12 Richard Biener * gimple.h (remove_pointer): New trait. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index bf0f84f5356..535a865e488 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -13615,7 +13615,7 @@ mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE) return false; - return !store_data_bypass_p (out_insn, in_insn); + return store_data_bypass_p (out_insn, in_insn); } diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md index 19b9b324653..e8d1f1b2da8 100644 --- a/gcc/config/mips/sb1.md +++ b/gcc/config/mips/sb1.md @@ -216,7 +216,7 @@ "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" - "mips_store_data_bypass_p") + "!mips_store_data_bypass_p") ;; On SB-1, simple alu instructions can execute on the LS1 unit. @@ -289,7 +289,7 @@ (define_bypass 5 "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" - "mips_store_data_bypass_p") + "!mips_store_data_bypass_p") ;; mf{hi,lo} is 1 cycle. @@ -351,7 +351,7 @@ (define_bypass 7 "ir_sb1_mulsi,ir_sb1_muldi" "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" - "mips_store_data_bypass_p") + "!mips_store_data_bypass_p") ;; The divide unit is not pipelined. Divide busy is asserted in the 4th ;; cycle, and then deasserted on the latency cycle. So only one divide at