From: lkcl <lkcl@web>
Date: Fri, 21 Apr 2023 14:03:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=58679ecdb99ec43a627103d0c036089884c49dee;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn
index 307db5a27..5dc568f3a 100644
--- a/openpower/sv/rfc/ls011.mdwn
+++ b/openpower/sv/rfc/ls011.mdwn
@@ -24,7 +24,8 @@ fit into one single Primary Opcode.  EXT2xx is recommended.
 
 One alternative idea is that bit 31 could be allocated (retrospectively)
 to Post-Increment.  Although it may be too late for Scalar Power ISA
-it **may** be possible to consider for SVP64Single and/or SVP64-Vector
+it **may** be possible to consider for SVP64Single and/or SVP64-Vector,
+but this risks creating a non-Orthogonal ISA.