From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 17 Jul 2020 15:21:30 +0000 (+0200)
Subject: Fix code styling
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=586eddd38b52faec12a3280b150933889d5b021d;p=gram.git

Fix code styling
---

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index e562d65..676fdb8 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -491,8 +491,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         # The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI
         # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies.
         rddata_en_last = Signal.like(rddata_en)
-        m.d.comb += rddata_en.eq(
-            Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last))
+        m.d.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last))
         m.d.sync += rddata_en_last.eq(rddata_en)
         m.d.sync += [phase.rddata_valid.eq(rddata_en[-1])
                      for phase in dfi.phases]