From: Gabe Black <gabeblack@google.com>
Date: Sun, 30 Aug 2020 08:29:18 +0000 (-0700)
Subject: mips,cpu: Get rid of the IsCondDelaySlot StaticInst flag.
X-Git-Tag: develop-gem5-snapshot~761
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=587c2e6a1cd03969c594efabc069b01681d58100;p=gem5.git

mips,cpu: Get rid of the IsCondDelaySlot StaticInst flag.

This is set by MIPS in a few places, but not actually used by anything.

Change-Id: Iaf3b29b2c14bb1de3ffd6a0035f12f238591cb60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33736
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
---

diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 4975a1321..7c2b27cc1 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -241,7 +241,6 @@ def format Branch(code, *opt_flags) {{
             code += 'R31 = NNPC;\n'
         elif x == 'Likely':
             not_taken_code = 'NNPC = NPC; NPC = PC;'
-            inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )
 
@@ -280,7 +279,6 @@ def format DspBranch(code, *opt_flags) {{
             code += 'R32 = NNPC;'
         elif x == 'Likely':
             not_taken_code = 'NNPC = NPC, NPC = PC;'
-            inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )
 
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 1c2b63a2b..5b8507b28 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -78,8 +78,6 @@ class StaticInstFlags(Enum):
         'IsCall',           # Subroutine call.
         'IsReturn',         # Subroutine return.
 
-        'IsCondDelaySlot',  # Conditional Delay-Slot Instruction
-
         'IsThreadSync',     # Thread synchronization operation.
 
         'IsSerializing',    # Serializes pipeline: won't execute until all
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index a6c08cc1f..60ca592cc 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -541,7 +541,6 @@ class BaseDynInst : public ExecContext, public RefCounted
     bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
     bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
     bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
-    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
     bool isThreadSync()   const { return staticInst->isThreadSync(); }
     bool isSerializing()  const { return staticInst->isSerializing(); }
     bool
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 146be8c72..1a0e42c36 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -179,7 +179,6 @@ class StaticInst : public RefCounted, public StaticInstFlags
     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
     bool isCondCtrl()     const { return flags[IsCondControl]; }
     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
-    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
 
     bool isThreadSync()   const { return flags[IsThreadSync]; }
     bool isSerializing()  const { return flags[IsSerializing] ||